gpu: nvgpu: split init_falcon_setup_hw

This CL is as part of phased changes to support NO LSPMU
Changes done are to add new pmu ops :
- setup_apertures
- update_lspmu_cmdline_args
These would be called from pmu op init_falcon_setup_hw

JIRA NVGPU-296

Change-Id: Idbcec5c93ca3150df5c9fb81d65b9fce778cecb8
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589004
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 20 insertions, 25 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
index b245dbc6..33a36596 100644
--- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
@@ -237,20 +237,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu,
         return 0;
 }
 
-int gv11b_init_pmu_setup_hw1(struct gk20a *g,
-                void *desc, u32 bl_sz)
+void gv11b_setup_apertures(struct gk20a *g)
 {
-
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err;
-
-        gk20a_dbg_fn("");
-
-        nvgpu_mutex_acquire(&pmu->isr_mutex);
-        nvgpu_flcn_reset(pmu->flcn);
-        pmu->isr_enabled = true;
-        nvgpu_mutex_release(&pmu->isr_mutex);
-
         /* setup apertures - virtual */
         gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
                         pwr_fbif_transcfg_mem_type_physical_f() |
@@ -267,19 +255,26 @@ int gv11b_init_pmu_setup_hw1(struct gk20a *g,
         gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
                         pwr_fbif_transcfg_mem_type_physical_f() |
                         pwr_fbif_transcfg_target_noncoherent_sysmem_f());
+}
+
+int gv11b_init_pmu_setup_hw1(struct gk20a *g,
+                void *desc, u32 bl_sz)
+{
+        struct nvgpu_pmu *pmu = &g->pmu;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        nvgpu_mutex_acquire(&pmu->isr_mutex);
+        nvgpu_flcn_reset(pmu->flcn);
+        pmu->isr_enabled = true;
+        nvgpu_mutex_release(&pmu->isr_mutex);
+
+        if (g->ops.pmu.setup_apertures)
+                g->ops.pmu.setup_apertures(g);
+        if (g->ops.pmu.update_lspmu_cmdline_args)
+                g->ops.pmu.update_lspmu_cmdline_args(g);
 
-        /*Copying pmu cmdline args*/
-        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
-                                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
-        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
-                pmu, GK20A_PMU_TRACE_BUFSIZE);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
-                pmu, GK20A_PMU_DMAIDX_VIRT);
-        nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
-                        (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
-                        g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
         /*disable irqs for hs falcon booting as we will poll for halt*/
         nvgpu_mutex_acquire(&pmu->isr_mutex);
         pmu_enable_irq(pmu, false);