gpu: nvgpu: use chip specific zbc_c/z format reg

Use chip specific gpcs_swdx_dss_zbc_c_format_reg
and gpcs_swdx_dss_zbc_z_format_reg. These registers
are different for gv11b/gv100 from gp10b/gp106.

Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 9c847a55..e935b2e5 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -1,7 +1,7 @@
 /*
  * GV100 Tegra HAL interface
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -314,6 +314,10 @@ static const struct gpu_ops gv100_ops = {
                 .detect_sm_arch = gr_gv11b_detect_sm_arch,
                 .add_zbc_color = gr_gp10b_add_zbc_color,
                 .add_zbc_depth = gr_gp10b_add_zbc_depth,
+                .get_gpcs_swdx_dss_zbc_c_format_reg =
+                        gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg,
+                .get_gpcs_swdx_dss_zbc_z_format_reg =
+                        gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg,
                 .zbc_set_table = gk20a_gr_zbc_set_table,
                 .zbc_query_table = gr_gk20a_query_zbc,
                 .pmu_save_zbc = gk20a_pmu_save_zbc,