diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-06-27 04:20:42 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-05 16:10:46 -0400 |
commit | e1161fe0e423d159ba7d5953d9be959ee96b4371 (patch) | |
tree | cfdbd9d3433af92b57f51909d3c9ee6bf4fdab9e /drivers/gpu/nvgpu/gv100 | |
parent | c7e1f6fe9409975544890993626964278b2c925c (diff) |
gpu: nvgpu: fix active fbpa mask calculation
In gr_gv100_get_active_fpba_mask(), we currently use num_fbpas passed by the
caller which is usually litter (max possible on h/w) value
We should instead read the number of FBPAs from h/w instead of reading litter
value
Jira NVGPUT-117
Change-Id: I6ecd4db0fd939e1dfebf31d27e0022ae02809399
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762721
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 2180fa1c..680bcba3 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c | |||
@@ -37,6 +37,7 @@ | |||
37 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> | 37 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> |
38 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | 38 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> |
39 | #include <nvgpu/hw/gv100/hw_fuse_gv100.h> | 39 | #include <nvgpu/hw/gv100/hw_fuse_gv100.h> |
40 | #include <nvgpu/hw/gv100/hw_top_gv100.h> | ||
40 | 41 | ||
41 | 42 | ||
42 | /* | 43 | /* |
@@ -371,9 +372,13 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g) | |||
371 | return size; | 372 | return size; |
372 | } | 373 | } |
373 | 374 | ||
374 | static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g, u32 num_fbpas) | 375 | static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g) |
375 | { | 376 | { |
376 | u32 active_fbpa_mask; | 377 | u32 active_fbpa_mask; |
378 | u32 num_fbpas, val; | ||
379 | |||
380 | val = nvgpu_readl(g, top_num_fbpas_r()); | ||
381 | num_fbpas = top_num_fbpas_value_v(val); | ||
377 | 382 | ||
378 | /* | 383 | /* |
379 | * Read active fbpa mask from fuse | 384 | * Read active fbpa mask from fuse |
@@ -404,7 +409,7 @@ int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g, | |||
404 | if ((cnt + (regs->count * num_fbpas)) > max_cnt) | 409 | if ((cnt + (regs->count * num_fbpas)) > max_cnt) |
405 | return -EINVAL; | 410 | return -EINVAL; |
406 | 411 | ||
407 | active_fbpa_mask = gr_gv100_get_active_fpba_mask(g, num_fbpas); | 412 | active_fbpa_mask = gr_gv100_get_active_fpba_mask(g); |
408 | 413 | ||
409 | for (idx = 0; idx < regs->count; idx++) { | 414 | for (idx = 0; idx < regs->count; idx++) { |
410 | for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) { | 415 | for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) { |
@@ -439,7 +444,7 @@ void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr, | |||
439 | u32 active_fbpa_mask; | 444 | u32 active_fbpa_mask; |
440 | u32 fbpa_id; | 445 | u32 fbpa_id; |
441 | 446 | ||
442 | active_fbpa_mask = gr_gv100_get_active_fpba_mask(g, num_fbpas); | 447 | active_fbpa_mask = gr_gv100_get_active_fpba_mask(g); |
443 | 448 | ||
444 | for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) { | 449 | for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) { |
445 | if (active_fbpa_mask & BIT(fbpa_id)) { | 450 | if (active_fbpa_mask & BIT(fbpa_id)) { |