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author | Thomas Fleury <tfleury@nvidia.com> | 2019-04-30 20:19:51 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-01-30 02:41:45 -0500 |
commit | dc281d6a9ebadaeb66dab092b40b7d6f4559ee39 (patch) | |
tree | cbe2c286c1549c2824eade89a25c033a86a7dd6e /drivers/gpu/nvgpu/gv100 | |
parent | 6e91ecaae77d769955e5e1f34ded90c064e9c245 (diff) |
gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl
Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
But 2713590
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
(cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9a3d2241..0e0417a0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 Tegra HAL interface | 2 | * GV100 Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -404,6 +404,7 @@ static const struct gpu_ops gv100_ops = { | |||
404 | .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, | 404 | .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, |
405 | .set_pmm_register = gr_gv100_set_pmm_register, | 405 | .set_pmm_register = gr_gv100_set_pmm_register, |
406 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 406 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
407 | .set_mmu_debug_mode = NULL, | ||
407 | .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, | 408 | .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, |
408 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 409 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
409 | .clear_sm_error_state = gv11b_gr_clear_sm_error_state, | 410 | .clear_sm_error_state = gv11b_gr_clear_sm_error_state, |
@@ -1040,6 +1041,7 @@ int gv100_init_hal(struct gk20a *g) | |||
1040 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); | 1041 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); |
1041 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); | 1042 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); |
1042 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); | 1043 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); |
1044 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | ||
1043 | 1045 | ||
1044 | /* for now */ | 1046 | /* for now */ |
1045 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 1047 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |