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| author | Alex Waterman <alexw@nvidia.com> | 2018-05-14 13:54:22 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-17 16:03:21 -0400 |
| commit | b4f8cd76e2de025a9bfb5a4836c52a95cd587faa (patch) | |
| tree | 546d0120b17a96689b42fd9192f2ffc3169f2d1e /drivers/gpu/nvgpu/gv100 | |
| parent | 4654d9abd176043e69d548d53d516e78e4054d9e (diff) | |
gpu: nvgpu: Update POSIX BIT() macro to ULL
For most of the builds we have in GVS userspace is 64 bits. But
it seems like at least some L4T userspace builds are either not
32 bits or have an UL that only covers 32 bits. This is seen in
GVS:
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gv11b/mm_gv11b.c: In function 'gv11b_gpu_phys_addr':
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:273:3: error: left shift count >= width of type
make[2]: *** [/dvs/git/dirty/git-master_modular/tmake/artifacts/CommonRules.tmk:318: mm_gv11b.o] Error 1
This patch simply bumps the UL to ULL in BIT() to make sure that
we always have at least 64 bits available for the BIT() macro.
JIRA NVGPU-525
Change-Id: I67de4338afc5bee4f1fa16faee6116e0e7dbf108
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1718564
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
0 files changed, 0 insertions, 0 deletions