diff options
author | Divya Singhatwaria <dsinghatwari@nvidia.com> | 2019-07-23 01:13:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2019-08-02 15:57:24 -0400 |
commit | ae175e45edc5807131dfb1b63d3e4795e96a3f86 (patch) | |
tree | c209caf5a5804f250be83e4a68295daa64d6cfb5 /drivers/gpu/nvgpu/gv100 | |
parent | 47f6bc0c2e85d0a8ff943b88c81108ca1bfc588e (diff) |
gpu: nvgpu: Use TPC_PG_MASK to powergate the TPC
- In GV11B, read fuse_status_opt_tpc_gpc register
to read which TPCs are floorswept.
- The driver will also read sysfs node: tpc_pg_mask
- Based on these two values "can_tpc_powergate" will
be set to true or false and mask will be used to write to
fuse_ctrl_opt_tpc_gpc register to powergate the TPC.
- can_tpc_powergate = true indicates that the mask value
sent from userspace is valid and can be used to power gate
the desired TPC
- can_tpc_powergate = false indicates that the mask value
sent from userspace is not valid and cannot be used to
power gate the desired TPC.
Bug 200532639
Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159219
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 457ae64c..6fd777c0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -971,6 +971,9 @@ static const struct gpu_ops gv100_ops = { | |||
971 | .acr = { | 971 | .acr = { |
972 | .acr_sw_init = nvgpu_gp106_acr_sw_init, | 972 | .acr_sw_init = nvgpu_gp106_acr_sw_init, |
973 | }, | 973 | }, |
974 | .tpc = { | ||
975 | .tpc_powergate = NULL, | ||
976 | }, | ||
974 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, | 977 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, |
975 | .get_litter_value = gv100_get_litter_value, | 978 | .get_litter_value = gv100_get_litter_value, |
976 | }; | 979 | }; |
@@ -1008,6 +1011,7 @@ int gv100_init_hal(struct gk20a *g) | |||
1008 | gops->falcon = gv100_ops.falcon; | 1011 | gops->falcon = gv100_ops.falcon; |
1009 | gops->priv_ring = gv100_ops.priv_ring; | 1012 | gops->priv_ring = gv100_ops.priv_ring; |
1010 | gops->fuse = gv100_ops.fuse; | 1013 | gops->fuse = gv100_ops.fuse; |
1014 | gops->tpc = gv100_ops.tpc; | ||
1011 | gops->nvlink = gv100_ops.nvlink; | 1015 | gops->nvlink = gv100_ops.nvlink; |
1012 | gops->top = gv100_ops.top; | 1016 | gops->top = gv100_ops.top; |
1013 | gops->acr = gv100_ops.acr; | 1017 | gops->acr = gv100_ops.acr; |