gpu: nvgpu: Simplify FB hub intr enable

Hard code flags for enabling and disabling FB hub interrupts.

JIRA NVGPU-714

Change-Id: I806ef443cb9e27e221d407d633ca91d8fb40d075
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769853
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 33 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c
index defb6642..1889268f 100644
--- a/drivers/gpu/nvgpu/gv100/fb_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c
@@ -70,6 +70,34 @@ void gv100_fb_reset(struct gk20a *g)
         gk20a_writel(g, fb_mmu_priv_level_mask_r(), val);
 }
 
+void gv100_fb_enable_hub_intr(struct gk20a *g)
+{
+        u32 mask = 0;
+
+        mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
+                        fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
+                        fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
+                        fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
+                        fb_niso_intr_en_set_mmu_replayable_fault_overflow_m();
+
+        gk20a_writel(g, fb_niso_intr_en_set_r(0),
+                        mask);
+}
+
+void gv100_fb_disable_hub_intr(struct gk20a *g)
+{
+        u32 mask = 0;
+
+        mask = fb_niso_intr_en_set_mmu_other_fault_notify_m() |
+                        fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() |
+                        fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m() |
+                        fb_niso_intr_en_set_mmu_replayable_fault_notify_m() |
+                        fb_niso_intr_en_set_mmu_replayable_fault_overflow_m();
+
+        gk20a_writel(g, fb_niso_intr_en_clr_r(0),
+                        mask);
+}
+
 int gv100_fb_memory_unlock(struct gk20a *g)
 {
         struct nvgpu_firmware *mem_unlock_fw = NULL;
diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h
index 5b99fe5e..195baccf 100644
--- a/drivers/gpu/nvgpu/gv100/fb_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h
@@ -28,6 +28,8 @@
 struct gk20a;
 
 void gv100_fb_reset(struct gk20a *g);
+void gv100_fb_enable_hub_intr(struct gk20a *g);
+void gv100_fb_disable_hub_intr(struct gk20a *g);
 int gv100_fb_memory_unlock(struct gk20a *g);
 int gv100_fb_init_nvlink(struct gk20a *g);
 int gv100_fb_enable_nvlink(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 3cfda7ca..ea131822 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -459,7 +459,7 @@ static const struct gpu_ops gv100_ops = {
         },
         .fb = {
                 .reset = gv100_fb_reset,
-                .init_hw = gk20a_fb_init_hw,
+                .init_hw = gv11b_fb_init_hw,
                 .init_fs_state = NULL,
                 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
                 .set_use_full_comp_tag_line =
@@ -481,8 +481,8 @@ static const struct gpu_ops gv100_ops = {
                 .mem_unlock = gv100_fb_memory_unlock,
                 .init_nvlink = gv100_fb_init_nvlink,
                 .enable_nvlink = gv100_fb_enable_nvlink,
-                .enable_hub_intr = gv11b_fb_enable_hub_intr,
-                .disable_hub_intr = gv11b_fb_disable_hub_intr,
+                .enable_hub_intr = gv100_fb_enable_hub_intr,
+                .disable_hub_intr = gv100_fb_disable_hub_intr,
                 .write_mmu_fault_buffer_lo_hi =
                                 fb_gv11b_write_mmu_fault_buffer_lo_hi,
                 .write_mmu_fault_buffer_get =
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c
index 7ed9e6da..3d6f0bd3 100644
--- a/drivers/gpu/nvgpu/gv100/mc_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/mc_gv100.c
@@ -41,7 +41,6 @@ void mc_gv100_intr_enable(struct gk20a *g)
                                 0xffffffffU);
         gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
                                 0xffffffffU);
-        g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
 
         g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
                                 mc_intr_pfifo_pending_f() |
@@ -56,9 +55,6 @@ void mc_gv100_intr_enable(struct gk20a *g)
                                 mc_intr_pfifo_pending_f()
                              | eng_intr_mask;
 
-        /* TODO: Enable PRI faults for HUB ECC err intr */
-        g->ops.fb.enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types);
-
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
                         g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);