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author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-09-10 11:41:49 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-24 11:12:03 -0400 |
commit | 863b47064445b3dd5cdc354821c8d3d14deade33 (patch) | |
tree | 1e53f26c1549d1970d752f74ab82a4d55642620b /drivers/gpu/nvgpu/gv100 | |
parent | fdf77eda18b59c305d4dd8436d8b09d42ec4718a (diff) |
gpu: nvgpu: PMU init sequence change
-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
for PMU RTOS & does start PMU RTOS in secure & non-secure
based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
secured_pmu_start assignment for gp106 & gv100 to support
modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
to handle non secure PMU bootstrap, reused this method
for need chips.
JIRA NVGPU-1146
Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 45c3adb3..99ee2d10 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -757,6 +757,10 @@ static const struct gpu_ops gv100_ops = { | |||
757 | .get_irqdest = gk20a_pmu_get_irqdest, | 757 | .get_irqdest = gk20a_pmu_get_irqdest, |
758 | .alloc_super_surface = nvgpu_pmu_super_surface_alloc, | 758 | .alloc_super_surface = nvgpu_pmu_super_surface_alloc, |
759 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, | 759 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, |
760 | .update_lspmu_cmdline_args = | ||
761 | gp106_update_lspmu_cmdline_args, | ||
762 | .setup_apertures = gp106_pmu_setup_apertures, | ||
763 | .secured_pmu_start = gm20b_secured_pmu_start, | ||
760 | }, | 764 | }, |
761 | .clk = { | 765 | .clk = { |
762 | .init_clk_support = gp106_init_clk_support, | 766 | .init_clk_support = gp106_init_clk_support, |