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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-30 17:05:16 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-13 22:18:24 -0400
commit7ac0b046a538daa1a3532d3d5ae7cba1ef3295ba (patch)
tree79e42a4abe1e0c7d2918fa588f50061b90ee3e5f /drivers/gpu/nvgpu/gv100
parentbf14c2a0faf922073eaf72d490bf8bde8df1a5c7 (diff)
gpu: nvgpu: Move MC HAL to common
Move implementation of MC HAL to common/mc. Also bump gk20a implementation to gm20b. gk20a_mc_boot_0 was used via a HAL, but we have only one possible implementation. It also has to be anyway called directly to detect which HALs to assign, so make it a true common function. mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c so move it there. JIRA NVGPU-954 Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813519 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c17
-rw-r--r--drivers/gpu/nvgpu/gv100/mc_gv100.c91
-rw-r--r--drivers/gpu/nvgpu/gv100/mc_gv100.h31
3 files changed, 8 insertions, 131 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 4af237b0..d6ee0139 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -45,12 +45,15 @@
45#include "common/fuse/fuse_gp10b.h" 45#include "common/fuse/fuse_gp10b.h"
46#include "common/fuse/fuse_gp106.h" 46#include "common/fuse/fuse_gp106.h"
47#include "common/top/top_gv100.h" 47#include "common/top/top_gv100.h"
48#include "common/mc/mc_gm20b.h"
49#include "common/mc/mc_gp10b.h"
50#include "common/mc/mc_gv11b.h"
51#include "common/mc/mc_gv100.h"
48 52
49#include "gk20a/gk20a.h" 53#include "gk20a/gk20a.h"
50#include "gk20a/fifo_gk20a.h" 54#include "gk20a/fifo_gk20a.h"
51#include "gk20a/fecs_trace_gk20a.h" 55#include "gk20a/fecs_trace_gk20a.h"
52#include "gk20a/css_gr_gk20a.h" 56#include "gk20a/css_gr_gk20a.h"
53#include "gk20a/mc_gk20a.h"
54#include "gk20a/dbg_gpu_gk20a.h" 57#include "gk20a/dbg_gpu_gk20a.h"
55#include "gk20a/flcn_gk20a.h" 58#include "gk20a/flcn_gk20a.h"
56#include "gk20a/regops_gk20a.h" 59#include "gk20a/regops_gk20a.h"
@@ -74,7 +77,6 @@
74#include "gp106/flcn_gp106.h" 77#include "gp106/flcn_gp106.h"
75 78
76#include "gp10b/gr_gp10b.h" 79#include "gp10b/gr_gp10b.h"
77#include "gp10b/mc_gp10b.h"
78#include "gp10b/ce_gp10b.h" 80#include "gp10b/ce_gp10b.h"
79#include "gp10b/fifo_gp10b.h" 81#include "gp10b/fifo_gp10b.h"
80#include "gp10b/fecs_trace_gp10b.h" 82#include "gp10b/fecs_trace_gp10b.h"
@@ -85,7 +87,6 @@
85#include "gv11b/dbg_gpu_gv11b.h" 87#include "gv11b/dbg_gpu_gv11b.h"
86#include "gv11b/hal_gv11b.h" 88#include "gv11b/hal_gv11b.h"
87#include "gv11b/gr_gv11b.h" 89#include "gv11b/gr_gv11b.h"
88#include "gv11b/mc_gv11b.h"
89#include "gv11b/gv11b.h" 90#include "gv11b/gv11b.h"
90#include "gv11b/ce_gv11b.h" 91#include "gv11b/ce_gv11b.h"
91#include "gv11b/mm_gv11b.h" 92#include "gv11b/mm_gv11b.h"
@@ -102,7 +103,6 @@
102#include "gv100/flcn_gv100.h" 103#include "gv100/flcn_gv100.h"
103#include "gv100/gr_ctx_gv100.h" 104#include "gv100/gr_ctx_gv100.h"
104#include "gv100/gr_gv100.h" 105#include "gv100/gr_gv100.h"
105#include "gv100/mc_gv100.h"
106#include "gv100/mm_gv100.h" 106#include "gv100/mm_gv100.h"
107#include "gv100/pmu_gv100.h" 107#include "gv100/pmu_gv100.h"
108#include "gv100/nvlink_gv100.h" 108#include "gv100/nvlink_gv100.h"
@@ -805,11 +805,10 @@ static const struct gpu_ops gv100_ops = {
805 .intr_nonstall = mc_gp10b_intr_nonstall, 805 .intr_nonstall = mc_gp10b_intr_nonstall,
806 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, 806 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
807 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, 807 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
808 .isr_nonstall = mc_gk20a_isr_nonstall, 808 .isr_nonstall = gm20b_mc_isr_nonstall,
809 .enable = gk20a_mc_enable, 809 .enable = gm20b_mc_enable,
810 .disable = gk20a_mc_disable, 810 .disable = gm20b_mc_disable,
811 .reset = gk20a_mc_reset, 811 .reset = gm20b_mc_reset,
812 .boot_0 = gk20a_mc_boot_0,
813 .log_pending_intrs = mc_gp10b_log_pending_intrs, 812 .log_pending_intrs = mc_gp10b_log_pending_intrs,
814 .is_intr1_pending = mc_gp10b_is_intr1_pending, 813 .is_intr1_pending = mc_gp10b_is_intr1_pending,
815 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, 814 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c
deleted file mode 100644
index 069a012a..00000000
--- a/drivers/gpu/nvgpu/gv100/mc_gv100.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * GV100 master
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <nvgpu/types.h>
26#include <nvgpu/io.h>
27
28#include "gk20a/gk20a.h"
29
30#include "gp10b/mc_gp10b.h"
31
32#include "mc_gv100.h"
33
34#include <nvgpu/hw/gv100/hw_mc_gv100.h>
35
36void mc_gv100_intr_enable(struct gk20a *g)
37{
38 u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
39
40 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
41 0xffffffffU);
42 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
43 0xffffffffU);
44 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
45 mc_intr_pfifo_pending_f() |
46 mc_intr_hub_pending_f() |
47 mc_intr_priv_ring_pending_f() |
48 mc_intr_pbus_pending_f() |
49 mc_intr_ltc_pending_f() |
50 mc_intr_nvlink_pending_f() |
51 eng_intr_mask;
52
53 g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
54 mc_intr_pfifo_pending_f()
55 | eng_intr_mask;
56
57 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
58 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
59
60 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
61 g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
62
63}
64
65bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
66{
67 return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false);
68}
69
70bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
71 u32 *eng_intr_pending)
72{
73 u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
74 u32 stall_intr, eng_intr_mask;
75
76 eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
77 *eng_intr_pending = mc_intr_0 & eng_intr_mask;
78
79 stall_intr = mc_intr_pfifo_pending_f() |
80 mc_intr_hub_pending_f() |
81 mc_intr_priv_ring_pending_f() |
82 mc_intr_pbus_pending_f() |
83 mc_intr_ltc_pending_f() |
84 mc_intr_nvlink_pending_f();
85
86 nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
87 "mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
88 mc_intr_0 & stall_intr, *eng_intr_pending);
89
90 return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
91}
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.h b/drivers/gpu/nvgpu/gv100/mc_gv100.h
deleted file mode 100644
index e9069258..00000000
--- a/drivers/gpu/nvgpu/gv100/mc_gv100.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef MC_GV100_H
24#define MC_GV100_H
25struct gk20a;
26
27void mc_gv100_intr_enable(struct gk20a *g);
28bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0);
29bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
30 u32 *eng_intr_pending);
31#endif