gpu: nvgpu: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces
including single statement loop bodies. This patch fix the MISRA
violations due to single statement loop bodies without braces by adding
them.

JIRA NVGPU-989

Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791194
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c
index 97affdd9..13092f2a 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c
@@ -229,9 +229,11 @@ int gr_gv100_init_sm_id_table(struct gk20a *g)
                 goto exit_build_table;
         }
 
-        for (gpc = 0; gpc < g->gr.gpc_count; gpc++)
-                for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++)
+        for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
+                for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++) {
                         gpc_tpc_mask[gpc] |= g->gr.pes_tpc_mask[pes][gpc];
+                }
+        }
 
         for (gtpc = 0; gtpc < g->gr.tpc_count; gtpc++) {
                 maxperf = -1;