gpu: nvgpu: Add gv11b_gr_clear_sm_error_state

All chips were currently using gm20b_gr_clear_sm_error_state
It was wrong for chips based on volta and later as the implementation didn't
consider non pes-aware vsms mapping

Add new HAL implementation for clear_sm_error_state for volta based and later
chips to fix this.

Bug 200448172

Change-Id: I65988c8cbb35d13089ac628e8333d9a3b58e0eb1
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837188
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 4f50b13f..2a381f55 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -383,7 +383,7 @@ static const struct gpu_ops gv100_ops = {
                 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
                 .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register,
                 .record_sm_error_state = gv11b_gr_record_sm_error_state,
-                .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
+                .clear_sm_error_state = gv11b_gr_clear_sm_error_state,
                 .suspend_contexts = gr_gp10b_suspend_contexts,
                 .resume_contexts = gr_gk20a_resume_contexts,
                 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,