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authorDeepak Nibade <dnibade@nvidia.com>2018-09-04 07:07:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-05 23:41:36 -0400
commit2998ab4e0a0b19da1332b82d779bd17b4e284b38 (patch)
treee86e3201c1920f8cb0afecdb6e21f9c0bf8de366 /drivers/gpu/nvgpu/gv100
parent2b2bde04e14135cae5f7433c755e6b8d70f88abb (diff)
gpu: nvgpu: remove unused regops HALs
Below regops HALs are not being called from anywhere, so remove them gops.regops.get_runcontrol_whitelist_ranges() gops.regops.get_runcontrol_whitelist_ranges_count() gops.regops.get_qctl_whitelist_ranges() gops.regops.get_qctl_whitelist_ranges_count() HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it was originally only needed for gk20a which is not unsupported So remove this HAL and its call too Jira NVGPU-620 Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c8
-rw-r--r--drivers/gpu/nvgpu/gv100/regops_gv100.c39
2 files changed, 0 insertions, 47 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 1bc5d091..9d90d1d4 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -790,16 +790,8 @@ static const struct gpu_ops gv100_ops = {
790 .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist, 790 .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist,
791 .get_runcontrol_whitelist_count = 791 .get_runcontrol_whitelist_count =
792 gv100_get_runcontrol_whitelist_count, 792 gv100_get_runcontrol_whitelist_count,
793 .get_runcontrol_whitelist_ranges =
794 gv100_get_runcontrol_whitelist_ranges,
795 .get_runcontrol_whitelist_ranges_count =
796 gv100_get_runcontrol_whitelist_ranges_count,
797 .get_qctl_whitelist = gv100_get_qctl_whitelist, 793 .get_qctl_whitelist = gv100_get_qctl_whitelist,
798 .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count, 794 .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count,
799 .get_qctl_whitelist_ranges = gv100_get_qctl_whitelist_ranges,
800 .get_qctl_whitelist_ranges_count =
801 gv100_get_qctl_whitelist_ranges_count,
802 .apply_smpc_war = gv100_apply_smpc_war,
803 }, 795 },
804 .mc = { 796 .mc = {
805 .intr_mask = mc_gp10b_intr_mask, 797 .intr_mask = mc_gp10b_intr_mask,
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c
index c6ce6b94..baf57c78 100644
--- a/drivers/gpu/nvgpu/gv100/regops_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include "gk20a/gk20a.h" 25#include "gk20a/gk20a.h"
26#include "gk20a/dbg_gpu_gk20a.h"
27#include "gk20a/regops_gk20a.h" 26#include "gk20a/regops_gk20a.h"
28#include "regops_gv100.h" 27#include "regops_gv100.h"
29 28
@@ -5626,19 +5625,12 @@ static const struct regop_offset_range gv100_global_whitelist_ranges[] = {
5626static const u64 gv100_global_whitelist_ranges_count = 5625static const u64 gv100_global_whitelist_ranges_count =
5627 ARRAY_SIZE(gv100_global_whitelist_ranges); 5626 ARRAY_SIZE(gv100_global_whitelist_ranges);
5628 5627
5629/* context */
5630
5631/* runcontrol */ 5628/* runcontrol */
5632static const u32 gv100_runcontrol_whitelist[] = { 5629static const u32 gv100_runcontrol_whitelist[] = {
5633}; 5630};
5634static const u64 gv100_runcontrol_whitelist_count = 5631static const u64 gv100_runcontrol_whitelist_count =
5635 ARRAY_SIZE(gv100_runcontrol_whitelist); 5632 ARRAY_SIZE(gv100_runcontrol_whitelist);
5636 5633
5637static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = {
5638};
5639static const u64 gv100_runcontrol_whitelist_ranges_count =
5640 ARRAY_SIZE(gv100_runcontrol_whitelist_ranges);
5641
5642 5634
5643/* quad ctl */ 5635/* quad ctl */
5644static const u32 gv100_qctl_whitelist[] = { 5636static const u32 gv100_qctl_whitelist[] = {
@@ -5646,11 +5638,6 @@ static const u32 gv100_qctl_whitelist[] = {
5646static const u64 gv100_qctl_whitelist_count = 5638static const u64 gv100_qctl_whitelist_count =
5647 ARRAY_SIZE(gv100_qctl_whitelist); 5639 ARRAY_SIZE(gv100_qctl_whitelist);
5648 5640
5649static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = {
5650};
5651static const u64 gv100_qctl_whitelist_ranges_count =
5652 ARRAY_SIZE(gv100_qctl_whitelist_ranges);
5653
5654const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) 5641const struct regop_offset_range *gv100_get_global_whitelist_ranges(void)
5655{ 5642{
5656 return gv100_global_whitelist_ranges; 5643 return gv100_global_whitelist_ranges;
@@ -5681,16 +5668,6 @@ u64 gv100_get_runcontrol_whitelist_count(void)
5681 return gv100_runcontrol_whitelist_count; 5668 return gv100_runcontrol_whitelist_count;
5682} 5669}
5683 5670
5684const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void)
5685{
5686 return gv100_runcontrol_whitelist_ranges;
5687}
5688
5689u64 gv100_get_runcontrol_whitelist_ranges_count(void)
5690{
5691 return gv100_runcontrol_whitelist_ranges_count;
5692}
5693
5694const u32 *gv100_get_qctl_whitelist(void) 5671const u32 *gv100_get_qctl_whitelist(void)
5695{ 5672{
5696 return gv100_qctl_whitelist; 5673 return gv100_qctl_whitelist;
@@ -5700,19 +5677,3 @@ u64 gv100_get_qctl_whitelist_count(void)
5700{ 5677{
5701 return gv100_qctl_whitelist_count; 5678 return gv100_qctl_whitelist_count;
5702} 5679}
5703
5704const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void)
5705{
5706 return gv100_qctl_whitelist_ranges;
5707}
5708
5709u64 gv100_get_qctl_whitelist_ranges_count(void)
5710{
5711 return gv100_qctl_whitelist_ranges_count;
5712}
5713
5714int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
5715{
5716 /* Not needed on gv100 */
5717 return 0;
5718}