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authorTejal Kudav <tkudav@nvidia.com>2018-06-04 03:45:28 -0400
committerTejal Kudav <tkudav@nvidia.com>2018-06-14 09:44:07 -0400
commit118b7fb891e976d7f5e8845b08d90f33d7e3043e (patch)
tree4bbd0606f86186a4939f3aa643b389b6518f6624 /drivers/gpu/nvgpu/gv100
parenta3356b8ad7ce625c02d7679aefe64185c84fe9a7 (diff)
gpu: nvgpu: nvlink: Add HAL to get link_mask
VBIOS link_disable_mask should be sufficient to find the connected links. As VBIOS is not updated with correct mask, we parse the DT node where we hardcode the link_id. DT method is not scalable as same DT node is used for different dGPUs connected over PCIE. Remove the DT parsing of link id and use HAL to get link_mask based on the GPU. JIRA NVLINK-162 Change-Id: Idb7b639962928ce48711a0d7fc277c4c324bee91 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1738967 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100')
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c1
-rw-r--r--drivers/gpu/nvgpu/gv100/nvlink_gv100.c23
-rw-r--r--drivers/gpu/nvgpu/gv100/nvlink_gv100.h3
3 files changed, 24 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 5e42ba9f..92900421 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -843,6 +843,7 @@ static const struct gpu_ops gv100_ops = {
843 .rxdet = NULL, 843 .rxdet = NULL,
844 .setup_pll = gv100_nvlink_setup_pll, 844 .setup_pll = gv100_nvlink_setup_pll,
845 .minion_data_ready_en = gv100_nvlink_minion_data_ready_en, 845 .minion_data_ready_en = gv100_nvlink_minion_data_ready_en,
846 .get_connected_link_mask = gv100_nvlink_get_connected_link_mask,
846 /* API */ 847 /* API */
847 .link_early_init = gv100_nvlink_link_early_init, 848 .link_early_init = gv100_nvlink_link_early_init,
848 .link_get_state = gv100_nvlink_link_get_state, 849 .link_get_state = gv100_nvlink_link_get_state,
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
index cae4f9bd..e85b5a93 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
@@ -2696,6 +2696,13 @@ u32 gv100_nvlink_link_get_rx_sublink_state(struct gk20a *g, u32 link_id)
2696 return nvl_sl1_slsm_status_rx_primary_state_v(reg); 2696 return nvl_sl1_slsm_status_rx_primary_state_v(reg);
2697} 2697}
2698 2698
2699/* Hardcode the link_mask while we wait for VBIOS link_disable_mask field
2700 * to be updated.
2701 */
2702void gv100_nvlink_get_connected_link_mask(u32 *link_mask)
2703{
2704 *link_mask = GV100_CONNECTED_LINK_MASK;
2705}
2699/* 2706/*
2700 * Performs nvlink device level initialization by discovering the topology 2707 * Performs nvlink device level initialization by discovering the topology
2701 * taking device out of reset, boot minion, set clocks up and common interrupts 2708 * taking device out of reset, boot minion, set clocks up and common interrupts
@@ -2735,10 +2742,20 @@ int gv100_nvlink_early_init(struct gk20a *g)
2735 /* Links in reset should be removed from initialized link sw state */ 2742 /* Links in reset should be removed from initialized link sw state */
2736 g->nvlink.initialized_links &= __gv100_nvlink_get_link_reset_mask(g); 2743 g->nvlink.initialized_links &= __gv100_nvlink_get_link_reset_mask(g);
2737 2744
2738 nvgpu_log(g, gpu_dbg_nvlink, "connected_links = 0x%08x (from DT)", 2745 /* VBIOS link_disable_mask should be sufficient to find the connected
2739 g->nvlink.connected_links); 2746 * links. As VBIOS is not updated with correct mask, we parse the DT
2747 * node where we hardcode the link_id. DT method is not scalable as same
2748 * DT node is used for different dGPUs connected over PCIE.
2749 * Remove the DT parsing of link id and use HAL to get link_mask based
2750 * on the GPU. This is temporary WAR while we get the VBIOS updated with
2751 * correct mask.
2752 */
2753 g->ops.nvlink.get_connected_link_mask(&(g->nvlink.connected_links));
2754
2755 nvgpu_log(g, gpu_dbg_nvlink, "connected_links = 0x%08x",
2756 g->nvlink.connected_links);
2740 2757
2741 /* Track unconnected links */ 2758 /* Track only connected links */
2742 g->nvlink.discovered_links &= g->nvlink.connected_links; 2759 g->nvlink.discovered_links &= g->nvlink.connected_links;
2743 2760
2744 nvgpu_log(g, gpu_dbg_nvlink, "discovered_links = 0x%08x (combination)", 2761 nvgpu_log(g, gpu_dbg_nvlink, "discovered_links = 0x%08x (combination)",
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.h b/drivers/gpu/nvgpu/gv100/nvlink_gv100.h
index bf923d4b..d9a4b073 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.h
@@ -23,6 +23,8 @@
23#ifndef NVGPU_NVLINK_GV100_H 23#ifndef NVGPU_NVLINK_GV100_H
24#define NVGPU_NVLINK_GV100_H 24#define NVGPU_NVLINK_GV100_H
25 25
26#define GV100_CONNECTED_LINK_MASK 0x8
27
26struct gk20a; 28struct gk20a;
27 29
28int gv100_nvlink_discover_ioctrl(struct gk20a *g); 30int gv100_nvlink_discover_ioctrl(struct gk20a *g);
@@ -34,6 +36,7 @@ int gv100_nvlink_minion_send_command(struct gk20a *g, u32 link_id, u32 command,
34int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask); 36int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask);
35int gv100_nvlink_minion_data_ready_en(struct gk20a *g, 37int gv100_nvlink_minion_data_ready_en(struct gk20a *g,
36 unsigned long link_mask, bool sync); 38 unsigned long link_mask, bool sync);
39void gv100_nvlink_get_connected_link_mask(u32 *link_mask);
37/* API */ 40/* API */
38int gv100_nvlink_link_early_init(struct gk20a *g, unsigned long mask); 41int gv100_nvlink_link_early_init(struct gk20a *g, unsigned long mask);
39u32 gv100_nvlink_link_get_mode(struct gk20a *g, u32 link_id); 42u32 gv100_nvlink_link_get_mode(struct gk20a *g, u32 link_id);