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authorTejal Kudav <tkudav@nvidia.com>2018-06-03 06:40:17 -0400
committerTejal Kudav <tkudav@nvidia.com>2018-06-14 09:44:07 -0400
commita3356b8ad7ce625c02d7679aefe64185c84fe9a7 (patch)
treea2124aa0e9ba9d131a3c126c2ed10eb817827c65 /drivers/gpu/nvgpu/gv100/nvlink_gv100.c
parent25fc64b944d12c007771efe24badda78be4e4cb7 (diff)
gpu: nvgpu: nvlink: Add HAL for minion INIT* dlcmd
The sequence of INIT* minion dlcmd varies between nvlink 2.0 and 2.2. The order is strict for 2.2. Also there are new dlcmds added to the nvlink bringup sequence. Add HAL to allow sequence update for nvlink 2.2. Old sequence: INITLANEENABLE-> INITDLPL New Sequence: INITDLPL->INITDLPL_TO_CHIPA->INITTL->INITLANEENABLE JIRA NVLINK-176 Change-Id: I49e0a726f56e7d6122ac4cddf0f0e021d16f1926 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1738329 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/nvlink_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/nvlink_gv100.c33
1 files changed, 16 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
index c87a3ce9..cae4f9bd 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
@@ -221,8 +221,6 @@ static const char *__gv100_device_type_to_str(u32 type)
221 */ 221 */
222static u32 __gv100_nvlink_get_link_reset_mask(struct gk20a *g); 222static u32 __gv100_nvlink_get_link_reset_mask(struct gk20a *g);
223static u32 gv100_nvlink_rxcal_en(struct gk20a *g, unsigned long mask); 223static u32 gv100_nvlink_rxcal_en(struct gk20a *g, unsigned long mask);
224static u32 gv100_nvlink_minion_data_ready_en(struct gk20a *g,
225 unsigned long mask, bool sync);
226 224
227 225
228/* 226/*
@@ -876,31 +874,32 @@ static u32 gv100_nvlink_minion_configure_ac_coupling(struct gk20a *g,
876/* 874/*
877 * Set Data ready 875 * Set Data ready
878 */ 876 */
879static u32 gv100_nvlink_minion_data_ready_en(struct gk20a *g, 877int gv100_nvlink_minion_data_ready_en(struct gk20a *g,
880 unsigned long mask, bool sync) 878 unsigned long link_mask, bool sync)
881{ 879{
882 u32 err = 0; 880 int ret = 0;
883 u32 i; 881 u32 link_id;
884 882
885 for_each_set_bit(i, &mask, 32) { 883 for_each_set_bit(link_id, &link_mask, 32) {
886 err = gv100_nvlink_minion_send_command(g, i, 884 ret = gv100_nvlink_minion_send_command(g, link_id,
887 minion_nvlink_dl_cmd_command_initlaneenable_v(), 0, 885 minion_nvlink_dl_cmd_command_initlaneenable_v(), 0,
888 sync); 886 sync);
889 if (err) { 887 if (ret) {
890 nvgpu_err(g, "Failed init lane enable on minion"); 888 nvgpu_err(g, "Failed initlaneenable on link %u",
891 return err; 889 link_id);
890 return ret;
892 } 891 }
893 } 892 }
894 893
895 for_each_set_bit(i, &mask, 32) { 894 for_each_set_bit(link_id, &link_mask, 32) {
896 err = gv100_nvlink_minion_send_command(g, i, 895 ret = gv100_nvlink_minion_send_command(g, link_id,
897 minion_nvlink_dl_cmd_command_initdlpl_v(), 0, sync); 896 minion_nvlink_dl_cmd_command_initdlpl_v(), 0, sync);
898 if (err) { 897 if (ret) {
899 nvgpu_err(g, "Failed init DLPL on minion"); 898 nvgpu_err(g, "Failed initdlpl on link %u", link_id);
900 return err; 899 return ret;
901 } 900 }
902 } 901 }
903 return err; 902 return ret;
904} 903}
905 904
906/* 905/*