gpu: nvgpu: Update gv100 nvlink TLC buffer config

TLC buffer sizes and credit init values do not match with
the values recommended by IAS for dGPU-Xavier configuration.
These buffer configuration values affect the latency over link.

JIRA NVLINK-158

Change-Id: I7822747cb0ae5a5efdd2d57e2104d0cb30bf9352
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1686601
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 23 insertions, 23 deletions

diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
index 10e7b149..e5e16e13 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
@@ -103,37 +103,37 @@ struct __nvlink_reginit {
 static const struct __nvlink_reginit  __nvlink_reginit_per_link_tegra[] = {
         /* NVTLC when connected to Tegra */
         { 0x300U, 0x00800040U },
-        { 0x304U, 0x00000020U },
-        { 0x308U, 0x00000020U },
-        { 0x30CU, 0x00000020U },
-        { 0x310U, 0x00000020U },
+        { 0x304U, 0x00000000U },
+        { 0x308U, 0x00000000U },
+        { 0x30CU, 0x00000000U },
+        { 0x310U, 0x00000000U },
         { 0x314U, 0x00800040U },
         { 0x318U, 0x00000000U },
         { 0x31CU, 0x00000000U },
         { 0x200U, 0x007F003FU },
-        { 0x204U, 0x007F005FU },
-        { 0x208U, 0x007F007FU },
-        { 0x20CU, 0x007F009FU },
-        { 0x210U, 0x007F00BFU },
-        { 0x214U, 0x00FF003FU },
-        { 0x218U, 0x00FF003FU },
-        { 0x21CU, 0x00FF003FU },
-        { 0xB00U, 0x010000BEU },
-        { 0xB04U, 0x00000064U },
+        { 0x204U, 0x007F003FU },
+        { 0x208U, 0x007F003FU },
+        { 0x20CU, 0x007F003FU },
+        { 0x210U, 0x007F003FU },
+        { 0x214U, 0x00FF007FU },
+        { 0x218U, 0x00FF007FU },
+        { 0x21CU, 0x00FF007FU },
+        { 0xB00U, 0x010000C0U },
+        { 0xB04U, 0x00000000U },
         { 0xB08U, 0x00000000U },
-        { 0xB0CU, 0x00000020U },
+        { 0xB0CU, 0x00000000U },
         { 0xB10U, 0x00000000U },
-        { 0xB14U, 0x010000BEU },
+        { 0xB14U, 0x010000C0U },
         { 0xB18U, 0x00000000U },
         { 0xB1CU, 0x00000000U },
-        { 0xA00U, 0x00FF00BDU },
-        { 0xA04U, 0x00FF0121U },
-        { 0xA08U, 0x00FF0121U },
-        { 0xA0CU, 0x00FF0141U },
-        { 0xA10U, 0x00FF0141U },
-        { 0xA14U, 0x01FF01FFU },
-        { 0xA18U, 0x01FF01FFU },
-        { 0xA1CU, 0x01FF01FFU },
+        { 0xA00U, 0x00FF00BFU },
+        { 0xA04U, 0x00FF00BFU },
+        { 0xA08U, 0x00FF00BFU },
+        { 0xA0CU, 0x00FF00BFU },
+        { 0xA10U, 0x00FF00BFU },
+        { 0xA14U, 0x01FF017FU },
+        { 0xA18U, 0x01FF017FU },
+        { 0xA1CU, 0x01FF017FU },
         { 0xF04U, 0x00FFFFFFU },
         { 0xF0CU, 0x00FFFFFFU },
         { 0xF1CU, 0x003FFFFFU },