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| author | Deepak Nibade <dnibade@nvidia.com> | 2018-05-28 20:21:12 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-30 14:56:42 -0400 |
| commit | 4607098c3a889b815dc85035649856f225fffb0b (patch) | |
| tree | b557958bdbb5f2ebf889c7ebe72576dd227e6616 /drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |
| parent | 5716d89482c30bb1cb731138cac0b8747e2995c6 (diff) | |
gpu: nvgpu: support CAU ctxsw list
CAU (Counter Aggregation Unit) registers might be split out from SMPC registers
and moved into their own list on some platforms
In gr_gk20a_init_ctx_vars_fw() add support to check if pm_cau list is available
If list is available, count will be set to non-zero here
In add_ctxsw_buffer_map_entries_gpcs(), parse the pm_cau list if count is
non-zero
Bug 2139870
Change-Id: Ia630e7d03481a6f927c6739d28ebfe49f221326f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1733208
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Braun (SW-GPU) <matthewb@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/nvlink_gv100.c')
0 files changed, 0 insertions, 0 deletions