diff options
author | Vinod G <vinodg@nvidia.com> | 2018-05-16 13:43:13 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-18 17:53:58 -0400 |
commit | ac687c95d383c3fb0165e6535893510409559a8e (patch) | |
tree | 7a76099c05186ad636704c07c5409bbc8547f20f /drivers/gpu/nvgpu/gv100/mc_gv100.c | |
parent | de67fb18fb639b7a605c77eeb2e1c639a8a3d67e (diff) |
gpu: nvgpu: Code updates for MISRA violations
Code related to MC module is updated for handling
MISRA violations
Rule 10.1: Operands shalln't be an inappropriate
essential type.
Rule 10.3: Value of expression shalln't be assigned
to an object with a narrow essential type.
Rule 10.4: Both operands in an operator shall have
the same essential type.
Rule 14.4: Controlling if statement shall have
essentially Boolean type.
Rule 15.6: Enclose if() sequences with braces.
JIRA NVGPU-646
JIRA NVGPU-659
JIRA NVGPU-671
Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1720926
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/mc_gv100.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/mc_gv100.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c index 5848a180..31dc97d9 100644 --- a/drivers/gpu/nvgpu/gv100/mc_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mc_gv100.c | |||
@@ -38,9 +38,9 @@ void mc_gv100_intr_enable(struct gk20a *g) | |||
38 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | 38 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); |
39 | 39 | ||
40 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | 40 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), |
41 | 0xffffffff); | 41 | 0xffffffffU); |
42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | 42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), |
43 | 0xffffffff); | 43 | 0xffffffffU); |
44 | gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); | 44 | gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); |
45 | 45 | ||
46 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = | 46 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = |
@@ -69,7 +69,7 @@ void mc_gv100_intr_enable(struct gk20a *g) | |||
69 | 69 | ||
70 | bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0) | 70 | bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0) |
71 | { | 71 | { |
72 | return ((mc_intr_0 & mc_intr_nvlink_pending_f()) ? true : false); | 72 | return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false); |
73 | } | 73 | } |
74 | 74 | ||
75 | bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) | 75 | bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) |
@@ -78,8 +78,9 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) | |||
78 | u32 stall_intr, eng_intr_mask; | 78 | u32 stall_intr, eng_intr_mask; |
79 | 79 | ||
80 | eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); | 80 | eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); |
81 | if (mc_intr_0 & eng_intr_mask) | 81 | if ((mc_intr_0 & eng_intr_mask) != 0U) { |
82 | return true; | 82 | return true; |
83 | } | ||
83 | 84 | ||
84 | stall_intr = mc_intr_pfifo_pending_f() | | 85 | stall_intr = mc_intr_pfifo_pending_f() | |
85 | mc_intr_hub_pending_f() | | 86 | mc_intr_hub_pending_f() | |
@@ -87,8 +88,9 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) | |||
87 | mc_intr_pbus_pending_f() | | 88 | mc_intr_pbus_pending_f() | |
88 | mc_intr_ltc_pending_f() | | 89 | mc_intr_ltc_pending_f() | |
89 | mc_intr_nvlink_pending_f(); | 90 | mc_intr_nvlink_pending_f(); |
90 | if (mc_intr_0 & stall_intr) | 91 | if ((mc_intr_0 & stall_intr) != 0U) { |
91 | return true; | 92 | return true; |
93 | } | ||
92 | 94 | ||
93 | return false; | 95 | return false; |
94 | } | 96 | } |