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authorDavid Nieto <dmartineznie@nvidia.com>2017-08-04 00:43:50 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-10-10 15:05:41 -0400
commitf518304e0d8102216c7c0022cd4b66fcd844264c (patch)
treefc6be25fb1f713654d5f725361bd1ecb722a085c /drivers/gpu/nvgpu/gv100/hal_gv100.c
parentbb1c38e2f5f133a4281f73f8076a206ec728bd22 (diff)
gpu: nvgpu: fix GV100 hal definitions
These changes allow GV100 to init the basic HALs to pass nvgpu_submit_twod (1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency issues (2) Properly enable FB (3) Fan control requires the execution of the pre-os FW, without it the SKU201 is extremely noisy JIRA: NVGPUGV100-9 Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1539926 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/hal_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c22
1 files changed, 16 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 028c9d84..7f7ab785 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -61,6 +61,7 @@
61#include "gp106/acr_gp106.h" 61#include "gp106/acr_gp106.h"
62#include "gp106/sec2_gp106.h" 62#include "gp106/sec2_gp106.h"
63#include "gp106/bios_gp106.h" 63#include "gp106/bios_gp106.h"
64#include "gv100/bios_gv100.h"
64#include "gp106/therm_gp106.h" 65#include "gp106/therm_gp106.h"
65#include "gp106/xve_gp106.h" 66#include "gp106/xve_gp106.h"
66#include "gp106/clk_gp106.h" 67#include "gp106/clk_gp106.h"
@@ -85,6 +86,10 @@
85#include "gv11b/mm_gv11b.h" 86#include "gv11b/mm_gv11b.h"
86#include "gv11b/pmu_gv11b.h" 87#include "gv11b/pmu_gv11b.h"
87#include "gv11b/fb_gv11b.h" 88#include "gv11b/fb_gv11b.h"
89#include "gv100/mm_gv100.h"
90#include "gv11b/pmu_gv11b.h"
91#include "gv100/fb_gv100.h"
92#include "gv100/fifo_gv100.h"
88#include "gv11b/fifo_gv11b.h" 93#include "gv11b/fifo_gv11b.h"
89#include "gv11b/gv11b_gating_reglist.h" 94#include "gv11b/gv11b_gating_reglist.h"
90#include "gv11b/regops_gv11b.h" 95#include "gv11b/regops_gv11b.h"
@@ -208,6 +213,11 @@ int gv100_init_gpu_characteristics(struct gk20a *g)
208 213
209 214
210static const struct gpu_ops gv100_ops = { 215static const struct gpu_ops gv100_ops = {
216 .bios = {
217 .init = gp106_bios_init,
218 .preos_wait_for_halt = gv100_bios_preos_wait_for_halt,
219 .preos_reload_check = gv100_bios_preos_reload_check,
220 },
211 .ltc = { 221 .ltc = {
212 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, 222 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
213 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, 223 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
@@ -218,7 +228,7 @@ static const struct gpu_ops gv100_ops = {
218 .init_comptags = gp10b_ltc_init_comptags, 228 .init_comptags = gp10b_ltc_init_comptags,
219 .cbc_ctrl = gm20b_ltc_cbc_ctrl, 229 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
220 .isr = gv11b_ltc_isr, 230 .isr = gv11b_ltc_isr,
221 .cbc_fix_config = gv11b_ltc_cbc_fix_config, 231 .cbc_fix_config = NULL,
222 .flush = gm20b_flush_ltc, 232 .flush = gm20b_flush_ltc,
223 .set_enabled = gp10b_ltc_set_enabled, 233 .set_enabled = gp10b_ltc_set_enabled,
224 }, 234 },
@@ -374,8 +384,7 @@ static const struct gpu_ops gv100_ops = {
374 .fb = { 384 .fb = {
375 .reset = gv100_fb_reset, 385 .reset = gv100_fb_reset,
376 .init_hw = gk20a_fb_init_hw, 386 .init_hw = gk20a_fb_init_hw,
377 .init_fs_state = gv11b_fb_init_fs_state, 387 .init_fs_state = NULL,
378 .init_cbc = gv11b_fb_init_cbc,
379 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 388 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
380 .set_use_full_comp_tag_line = 389 .set_use_full_comp_tag_line =
381 gm20b_fb_set_use_full_comp_tag_line, 390 gm20b_fb_set_use_full_comp_tag_line,
@@ -417,7 +426,7 @@ static const struct gpu_ops gv100_ops = {
417 .trigger_mmu_fault = NULL, 426 .trigger_mmu_fault = NULL,
418 .get_mmu_fault_info = NULL, 427 .get_mmu_fault_info = NULL,
419 .wait_engine_idle = gk20a_fifo_wait_engine_idle, 428 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
420 .get_num_fifos = gv11b_fifo_get_num_fifos, 429 .get_num_fifos = gv100_fifo_get_num_fifos,
421 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, 430 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
422 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, 431 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
423 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, 432 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
@@ -633,7 +642,6 @@ static const struct gpu_ops gv100_ops = {
633 }, 642 },
634 .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, 643 .chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
635 .get_litter_value = gv100_get_litter_value, 644 .get_litter_value = gv100_get_litter_value,
636 .bios_init = gp106_bios_init,
637}; 645};
638 646
639int gv100_init_hal(struct gk20a *g) 647int gv100_init_hal(struct gk20a *g)
@@ -641,6 +649,7 @@ int gv100_init_hal(struct gk20a *g)
641 struct gpu_ops *gops = &g->ops; 649 struct gpu_ops *gops = &g->ops;
642 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; 650 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
643 651
652 gops->bios = gv100_ops.bios;
644 gops->ltc = gv100_ops.ltc; 653 gops->ltc = gv100_ops.ltc;
645 gops->ce2 = gv100_ops.ce2; 654 gops->ce2 = gv100_ops.ce2;
646 gops->gr = gv100_ops.gr; 655 gops->gr = gv100_ops.gr;
@@ -674,7 +683,6 @@ int gv100_init_hal(struct gk20a *g)
674 gops->chip_init_gpu_characteristics = 683 gops->chip_init_gpu_characteristics =
675 gv100_ops.chip_init_gpu_characteristics; 684 gv100_ops.chip_init_gpu_characteristics;
676 gops->get_litter_value = gv100_ops.get_litter_value; 685 gops->get_litter_value = gv100_ops.get_litter_value;
677 gops->bios_init = gv100_ops.bios_init;
678 686
679 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); 687 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
680 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); 688 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
@@ -689,6 +697,8 @@ int gv100_init_hal(struct gk20a *g)
689 gv11b_init_uncompressed_kind_map(); 697 gv11b_init_uncompressed_kind_map();
690 gv11b_init_kind_attr(); 698 gv11b_init_kind_attr();
691 699
700 g->bootstrap_owner = LSF_FALCON_ID_SEC2;
701
692 g->name = "gv10x"; 702 g->name = "gv10x";
693 703
694 c->twod_class = FERMI_TWOD_A; 704 c->twod_class = FERMI_TWOD_A;