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author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-09-12 17:51:40 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-27 18:05:25 -0400 |
commit | e3ae03e17abd452c157545234348692364b4b9f6 (patch) | |
tree | 121b3dcde56c87f9a1008ad4f5effbeb69cff945 /drivers/gpu/nvgpu/gv100/hal_gv100.c | |
parent | 78e3d22da3c2513d425c8c2560468ce854a982dd (diff) |
gpu: nvgpu: Add MC APIs for reset masks
Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.
JIRA NVGPU-954
Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/hal_gv100.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index da89d2b5..aae2bf73 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -817,6 +817,8 @@ static const struct gpu_ops gv100_ops = { | |||
817 | .is_intr_nvlink_pending = gv100_mc_is_intr_nvlink_pending, | 817 | .is_intr_nvlink_pending = gv100_mc_is_intr_nvlink_pending, |
818 | .is_stall_and_eng_intr_pending = | 818 | .is_stall_and_eng_intr_pending = |
819 | gv100_mc_is_stall_and_eng_intr_pending, | 819 | gv100_mc_is_stall_and_eng_intr_pending, |
820 | .reset_mask = gv100_mc_reset_mask, | ||
821 | .is_enabled = gm20b_mc_is_enabled, | ||
820 | }, | 822 | }, |
821 | .debug = { | 823 | .debug = { |
822 | .show_dump = gk20a_debug_show_dump, | 824 | .show_dump = gk20a_debug_show_dump, |