gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl

Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.

Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.

Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.

Bug 2515097
But 2713590

Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
(cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 9a3d2241..0e0417a0 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -1,7 +1,7 @@
 /*
  * GV100 Tegra HAL interface
  *
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -404,6 +404,7 @@ static const struct gpu_ops gv100_ops = {
                 .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon,
                 .set_pmm_register = gr_gv100_set_pmm_register,
                 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
+                .set_mmu_debug_mode = NULL,
                 .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register,
                 .record_sm_error_state = gv11b_gr_record_sm_error_state,
                 .clear_sm_error_state = gv11b_gr_clear_sm_error_state,
@@ -1040,6 +1041,7 @@ int gv100_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
         __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
         __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
+        __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false);
 
         /* for now */
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);