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authorVaikundanathan S <vaikuns@nvidia.com>2018-08-28 02:28:25 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-20 13:50:53 -0400
commitae809fddbe90bcec0d48e1213fa36cc5ba76550d (patch)
treebbafc71a543abf4b02e76290d058719f27f5f3b8 /drivers/gpu/nvgpu/gv100/hal_gv100.c
parent85c323c3e89d6e1b624b839c3325ae072952e545 (diff)
gpu:nvgpu: Add GV10x perf event
In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/hal_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index ee6dd436..0c64ce58 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -107,6 +107,7 @@
107#include "gv100/pmu_gv100.h" 107#include "gv100/pmu_gv100.h"
108#include "gv100/nvlink_gv100.h" 108#include "gv100/nvlink_gv100.h"
109#include "gv100/regops_gv100.h" 109#include "gv100/regops_gv100.h"
110#include "gv100/perf_gv100.h"
110 111
111#include <nvgpu/ptimer.h> 112#include <nvgpu/ptimer.h>
112#include <nvgpu/debug.h> 113#include <nvgpu/debug.h>
@@ -770,6 +771,7 @@ static const struct gpu_ops gv100_ops = {
770 .get_rate_cntr = gp106_get_rate_cntr, 771 .get_rate_cntr = gp106_get_rate_cntr,
771 .measure_freq = gp106_clk_measure_freq, 772 .measure_freq = gp106_clk_measure_freq,
772 .suspend_clk_support = gp106_suspend_clk_support, 773 .suspend_clk_support = gp106_suspend_clk_support,
774 .perf_pmu_vfe_load = gv100_perf_pmu_vfe_load,
773 }, 775 },
774 .clk_arb = { 776 .clk_arb = {
775 .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, 777 .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains,
@@ -981,6 +983,7 @@ int gv100_init_hal(struct gk20a *g)
981 gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; 983 gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz;
982 gops->clk.measure_freq = gv100_ops.clk.measure_freq; 984 gops->clk.measure_freq = gv100_ops.clk.measure_freq;
983 gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; 985 gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support;
986 gops->clk.perf_pmu_vfe_load = gv100_ops.clk.perf_pmu_vfe_load;
984 987
985 /* Lone functions */ 988 /* Lone functions */
986 gops->chip_init_gpu_characteristics = 989 gops->chip_init_gpu_characteristics =