gpu: nvgpu: Use TPC_PG_MASK to powergate the TPC

- In GV11B, read fuse_status_opt_tpc_gpc register
  to read which TPCs are floorswept.
- The driver will also read sysfs node: tpc_pg_mask
- Based on these two values "can_tpc_powergate" will
  be set to true or false and mask will be used to write to
  fuse_ctrl_opt_tpc_gpc register to powergate the TPC.
- can_tpc_powergate = true indicates that the mask value
  sent from userspace is valid and can be used to power gate
  the desired TPC
- can_tpc_powergate = false indicates that the mask value
  sent from userspace is not valid and cannot  be used to
  power gate the desired TPC.

Bug 200532639

Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159219
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 457ae64c..6fd777c0 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -971,6 +971,9 @@ static const struct gpu_ops gv100_ops = {
         .acr = {
                 .acr_sw_init = nvgpu_gp106_acr_sw_init,
         },
+        .tpc = {
+                .tpc_powergate = NULL,
+        },
         .chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
         .get_litter_value = gv100_get_litter_value,
 };
@@ -1008,6 +1011,7 @@ int gv100_init_hal(struct gk20a *g)
         gops->falcon = gv100_ops.falcon;
         gops->priv_ring = gv100_ops.priv_ring;
         gops->fuse = gv100_ops.fuse;
+        gops->tpc = gv100_ops.tpc;
         gops->nvlink = gv100_ops.nvlink;
         gops->top = gv100_ops.top;
         gops->acr = gv100_ops.acr;