gpu: nvgpu: gv11b: enable more gr exceptions

-pd, scc, ds, ssync, mme and sked exceptions are
 enabled. This will be useful for debugging
-Handle enabled interrupts
-Add gr ops to handle ssync hww. For legacy
 chips, ssync hww_esr register is gpcs_ppcs_ssync_hww_esr.
 Since ssync hww is not enabled on legacy chips, added
 ssync hww exception handling for volta only.

Change-Id: I63ba2eb51fa82e74832df26ee4cf3546458e5669
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644751
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index a2b97520..0f966adb 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -426,6 +426,7 @@ static const struct gpu_ops gv100_ops = {
                         gr_gv11b_handle_tpc_sm_ecc_exception,
                 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
                 .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable,
+                .handle_ssync_hww = gr_gv11b_handle_ssync_hww,
         },
         .fb = {
                 .reset = gv100_fb_reset,