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authorDavid Nieto <dmartineznie@nvidia.com>2017-10-19 13:12:24 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-10-23 01:15:22 -0400
commit6114553413297dbcae637bc50ef2ff2a6c0858d1 (patch)
treea32a295e5d13018fecff56f57684f3db51b1e532 /drivers/gpu/nvgpu/gv100/hal_gv100.c
parent2904e3ac0081d4e898378f6ba667658c85547368 (diff)
gpu: nvgpu: gv100: fix timeout handling
GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts need to be adjusted to avoid false positives. JIRA: NVGPUGV100-36 Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582092 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/hal_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 4e05f22b..ff852168 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -424,6 +424,7 @@ static const struct gpu_ops gv100_ops = {
424 .mem_unlock = gv100_fb_memory_unlock, 424 .mem_unlock = gv100_fb_memory_unlock,
425 }, 425 },
426 .fifo = { 426 .fifo = {
427 .get_preempt_timeout = gv100_fifo_get_preempt_timeout,
427 .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, 428 .init_fifo_setup_hw = gv11b_init_fifo_setup_hw,
428 .bind_channel = channel_gm20b_bind, 429 .bind_channel = channel_gm20b_bind,
429 .unbind_channel = channel_gv11b_unbind, 430 .unbind_channel = channel_gv11b_unbind,
@@ -470,7 +471,7 @@ static const struct gpu_ops gv100_ops = {
470 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, 471 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
471 .is_preempt_pending = gv11b_fifo_is_preempt_pending, 472 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
472 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, 473 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
473 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, 474 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
474 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, 475 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
475 .handle_sched_error = gv11b_fifo_handle_sched_error, 476 .handle_sched_error = gv11b_fifo_handle_sched_error,
476 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, 477 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
@@ -523,7 +524,7 @@ static const struct gpu_ops gv100_ops = {
523 .vm_bind_channel = gk20a_vm_bind_channel, 524 .vm_bind_channel = gk20a_vm_bind_channel,
524 .fb_flush = gk20a_mm_fb_flush, 525 .fb_flush = gk20a_mm_fb_flush,
525 .l2_invalidate = gk20a_mm_l2_invalidate, 526 .l2_invalidate = gk20a_mm_l2_invalidate,
526 .l2_flush = gv11b_mm_l2_flush, 527 .l2_flush = gk20a_mm_l2_flush,
527 .cbc_clean = gk20a_mm_cbc_clean, 528 .cbc_clean = gk20a_mm_cbc_clean,
528 .set_big_page_size = gm20b_mm_set_big_page_size, 529 .set_big_page_size = gm20b_mm_set_big_page_size,
529 .get_big_page_sizes = gm20b_mm_get_big_page_sizes, 530 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
@@ -542,6 +543,7 @@ static const struct gpu_ops gv100_ops = {
542 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, 543 .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup,
543 .remove_bar2_vm = gv11b_mm_remove_bar2_vm, 544 .remove_bar2_vm = gv11b_mm_remove_bar2_vm,
544 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, 545 .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy,
546 .get_flush_retries = gv100_mm_get_flush_retries,
545 }, 547 },
546 .pramin = { 548 .pramin = {
547 .enter = gk20a_pramin_enter, 549 .enter = gk20a_pramin_enter,