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authorSeema Khowala <seemaj@nvidia.com>2018-03-27 18:18:53 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-04-12 13:43:43 -0400
commit9fbfffbed024a46f3f94a54327e045e3830f4895 (patch)
tree50b9f6125249de20bcb2b79211a0c5446be22520 /drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c
parent040da8c01da0da58c4ca904b5d3a47298e94a001 (diff)
gpu: nvgpu: gv100: support clock gating
-Generated list for addr/value pairs using gen_gating_reglist.pl --target_ip=gv100 --soc=t194 -Comment out addresses triggering priv/pbus errors Bug 200399393 Change-Id: Ica0fd65070a7100f20afa32184f4a2e3cad6d0c2 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683101 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c')
-rw-r--r--drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c951
1 files changed, 951 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c b/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c
new file mode 100644
index 00000000..60ec0282
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c
@@ -0,0 +1,951 @@
1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 * This file is autogenerated. Do not edit.
22 */
23
24#ifndef __gv100_gating_reglist_h__
25#define __gv100_gating_reglist_h__
26
27#include <linux/types.h>
28#include "gv100_gating_reglist.h"
29
30struct gating_desc {
31 u32 addr;
32 u32 prod;
33 u32 disable;
34};
35/* slcg bus */
36static const struct gating_desc gv100_slcg_bus[] = {
37 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
38};
39
40/* slcg ce2 */
41static const struct gating_desc gv100_slcg_ce2[] = {
42 {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe},
43};
44
45/* slcg chiplet */
46static const struct gating_desc gv100_slcg_chiplet[] = {
47 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
48 {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007},
49 {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007},
50 {.addr = 0x0010c37c, .prod = 0x00000000, .disable = 0x00000007},
51 {.addr = 0x0010c47c, .prod = 0x00000000, .disable = 0x00000007},
52 {.addr = 0x0010c57c, .prod = 0x00000000, .disable = 0x00000007},
53 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
54 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
55 {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007},
56 {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007},
57 {.addr = 0x0010d37c, .prod = 0x00000000, .disable = 0x00000007},
58 {.addr = 0x0010d47c, .prod = 0x00000000, .disable = 0x00000007},
59 {.addr = 0x0010d57c, .prod = 0x00000000, .disable = 0x00000007},
60 /* fix priv error */
61 /*{.addr = 0x0010d67c, .prod = 0x00000000, .disable = 0x00000007},*/
62 /*{.addr = 0x0010d77c, .prod = 0x00000000, .disable = 0x00000007},*/
63 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
64};
65
66/* slcg fb */
67static const struct gating_desc gv100_slcg_fb[] = {
68 {.addr = 0x00100d14, .prod = 0x00000020, .disable = 0xfffffffe},
69 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
70 {.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe},
71};
72
73/* slcg fifo */
74static const struct gating_desc gv100_slcg_fifo[] = {
75 {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe},
76};
77
78/* slcg gr */
79static const struct gating_desc gv100_slcg_gr[] = {
80 {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe},
81 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
82 {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe},
83 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
84 {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe},
85 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
86 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
87 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
88 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
89 {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002},
90 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
91 {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe},
92 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
93 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
94 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
95 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe},
96 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
97 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
98 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
99 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
100 {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},
101 {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe},
102 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
103 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
104 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
105 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
106 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
107 {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff},
108 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
109 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
110 /* fix priv error */
111 /*{.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe},*/
112 {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe},
113 {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe},
114 {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe},
115 {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe},
116 {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e},
117 {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe},
118 {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e},
119 {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e},
120 {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe},
121 {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e},
122 {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e},
123 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
124 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
125 {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
126 {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe},
127 {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe},
128 {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe},
129 {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x000000ff},
130 {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe},
131 {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe},
132 {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe},
133 {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x000000ff},
134 /* fix priv error */
135 /*{.addr = 0x00413014, .prod = 0x00000000, .disable = 0x0001fffe},*/
136 /*{.addr = 0x00413284, .prod = 0x00000000, .disable = 0x0001fffe},*/
137 /*{.addr = 0x004131ac, .prod = 0x00000000, .disable = 0x0001fffe},*/
138 /*{.addr = 0x00413224, .prod = 0x00000000, .disable = 0x000000ff},*/
139 /*{.addr = 0x00413414, .prod = 0x00000000, .disable = 0x0001fffe},*/
140 /*{.addr = 0x00413684, .prod = 0x00000000, .disable = 0x0001fffe},*/
141 /*{.addr = 0x004135ac, .prod = 0x00000000, .disable = 0x0001fffe},*/
142 /*{.addr = 0x00413624, .prod = 0x00000000, .disable = 0x000000ff},*/
143 /*{.addr = 0x00413814, .prod = 0x00000000, .disable = 0x0001fffe},*/
144 /*{.addr = 0x00413a84, .prod = 0x00000000, .disable = 0x0001fffe},*/
145 /*{.addr = 0x004139ac, .prod = 0x00000000, .disable = 0x0001fffe},*/
146 /*{.addr = 0x00413a24, .prod = 0x00000000, .disable = 0x000000ff},*/
147 /*{.addr = 0x00413c14, .prod = 0x00000000, .disable = 0x0001fffe},*/
148 /*{.addr = 0x00413e84, .prod = 0x00000000, .disable = 0x0001fffe},*/
149 /*{.addr = 0x00413dac, .prod = 0x00000000, .disable = 0x0001fffe},*/
150 /*{.addr = 0x00413e24, .prod = 0x00000000, .disable = 0x000000ff},*/
151 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
152 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
153 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
154 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff},
155};
156
157/* slcg ltc */
158static const struct gating_desc gv100_slcg_ltc[] = {
159 {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe},
160 {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe},
161 {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe},
162 {.addr = 0x0015495c, .prod = 0x00000000, .disable = 0xfffffffe},
163 {.addr = 0x00154b5c, .prod = 0x00000000, .disable = 0xfffffffe},
164 {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe},
165 {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe},
166 {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe},
167 {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe},
168 {.addr = 0x0015695c, .prod = 0x00000000, .disable = 0xfffffffe},
169 {.addr = 0x00156b5c, .prod = 0x00000000, .disable = 0xfffffffe},
170 {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe},
171 /* fix priv error */
172 /*{.addr = 0x00158050, .prod = 0x00000000, .disable = 0xfffffffe},*/
173 /*{.addr = 0x0015855c, .prod = 0x00000000, .disable = 0xfffffffe},*/
174 /*{.addr = 0x0015875c, .prod = 0x00000000, .disable = 0xfffffffe},*/
175 /*{.addr = 0x0015895c, .prod = 0x00000000, .disable = 0xfffffffe},*/
176 /*{.addr = 0x00158b5c, .prod = 0x00000000, .disable = 0xfffffffe},*/
177 /*{.addr = 0x0015835c, .prod = 0x00000000, .disable = 0xfffffffe},*/
178 /*{.addr = 0x0015a050, .prod = 0x00000000, .disable = 0xfffffffe},*/
179 /*{.addr = 0x0015a55c, .prod = 0x00000000, .disable = 0xfffffffe},*/
180 /*{.addr = 0x0015a75c, .prod = 0x00000000, .disable = 0xfffffffe},*/
181 /*{.addr = 0x0015a95c, .prod = 0x00000000, .disable = 0xfffffffe},*/
182 /*{.addr = 0x0015ab5c, .prod = 0x00000000, .disable = 0xfffffffe},*/
183 /*{.addr = 0x0015a35c, .prod = 0x00000000, .disable = 0xfffffffe},*/
184 /*{.addr = 0x0015c050, .prod = 0x00000000, .disable = 0xfffffffe},*/
185 /*{.addr = 0x0015c55c, .prod = 0x00000000, .disable = 0xfffffffe},*/
186 /*{.addr = 0x0015c75c, .prod = 0x00000000, .disable = 0xfffffffe},*/
187 /*{.addr = 0x0015c95c, .prod = 0x00000000, .disable = 0xfffffffe},*/
188 /*{.addr = 0x0015cb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/
189 /*{.addr = 0x0015c35c, .prod = 0x00000000, .disable = 0xfffffffe},*/
190 /*{.addr = 0x0015e050, .prod = 0x00000000, .disable = 0xfffffffe},*/
191 /*{.addr = 0x0015e55c, .prod = 0x00000000, .disable = 0xfffffffe},*/
192 /*{.addr = 0x0015e75c, .prod = 0x00000000, .disable = 0xfffffffe},*/
193 /*{.addr = 0x0015e95c, .prod = 0x00000000, .disable = 0xfffffffe},*/
194 /*{.addr = 0x0015eb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/
195 /*{.addr = 0x0015e35c, .prod = 0x00000000, .disable = 0xfffffffe},*/
196 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
197 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
198};
199
200/* slcg perf */
201static const struct gating_desc gv100_slcg_perf[] = {
202 {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000},
203 {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000},
204 {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000},
205 {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000},
206 {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000},
207 {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000},
208 {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000},
209 {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000},
210 /* fix priv error */
211 /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/
212 /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/
213 {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000},
214 {.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000},
215 {.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000},
216 {.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000},
217 {.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000},
218 {.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000},
219 /* fix priv error */
220 /*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/
221 /*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/
222 {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000},
223 {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000},
224 {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000},
225 {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000},
226 {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000},
227 {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000},
228 {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000},
229 {.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000},
230 {.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000},
231 {.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000},
232 {.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000},
233 {.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000},
234 {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000},
235};
236
237/* slcg PriRing */
238static const struct gating_desc gv100_slcg_priring[] = {
239 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
240};
241
242/* slcg pwr_csb */
243static const struct gating_desc gv100_slcg_pwr_csb[] = {
244 {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe},
245 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
246 {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe},
247 {.addr = 0x000016b8, .prod = 0x00000008, .disable = 0x0000000f},
248};
249
250/* slcg pmu */
251static const struct gating_desc gv100_slcg_pmu[] = {
252 {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
253 {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe},
254 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
255};
256
257/* therm gr */
258static const struct gating_desc gv100_slcg_therm[] = {
259 {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f},
260};
261
262/* slcg Xbar */
263static const struct gating_desc gv100_slcg_xbar[] = {
264 {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe},
265 {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe},
266 {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe},
267 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
268 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
269 {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe},
270 {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe},
271 {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe},
272 {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe},
273 {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe},
274};
275
276/* blcg bus */
277static const struct gating_desc gv100_blcg_bus[] = {
278 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
279};
280
281/* blcg ce */
282static const struct gating_desc gv100_blcg_ce[] = {
283 {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000},
284};
285
286/* blcg ctxsw prog */
287static const struct gating_desc gv100_blcg_ctxsw_prog[] = {
288};
289
290/* blcg fb */
291static const struct gating_desc gv100_blcg_fb[] = {
292 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
293 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
294 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
295 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
296 /* fix priv error */
297 /*{.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},*/
298 {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
299 {.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000},
300};
301
302/* blcg fifo */
303static const struct gating_desc gv100_blcg_fifo[] = {
304 {.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000},
305};
306
307/* blcg gr */
308static const struct gating_desc gv100_blcg_gr[] = {
309 {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
310 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
311 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
312 {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
313 {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
314 {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
315 {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
316 {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
317 {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
318 {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
319 {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
320 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
321 {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
322 {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
323 {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
324 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
325 {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
326 {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
327 {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
328 {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
329 {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
330 {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
331 {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
332 {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000},
333 {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
334 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
335 {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
336 {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000},
337 {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
338 {.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000},
339 {.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000},
340 {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000},
341 {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000},
342 {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000},
343 {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000},
344 {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000},
345 {.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000},
346 {.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000},
347 {.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000},
348 {.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000},
349 {.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000},
350 {.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000},
351 {.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000},
352 {.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000},
353 {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
354 {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
355 {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
356 {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000},
357 {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000},
358 {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000},
359 {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000},
360 {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000},
361 {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000},
362 /* fix priv error */
363 /*{.addr = 0x00413010, .prod = 0x0000c242, .disable = 0x00000000},*/
364 /*{.addr = 0x00413280, .prod = 0x0000c242, .disable = 0x00000000},*/
365 /*{.addr = 0x004131a8, .prod = 0x0000c242, .disable = 0x00000000},*/
366 /*{.addr = 0x00413410, .prod = 0x0000c242, .disable = 0x00000000},*/
367 /*{.addr = 0x00413680, .prod = 0x0000c242, .disable = 0x00000000},*/
368 /*{.addr = 0x004135a8, .prod = 0x0000c242, .disable = 0x00000000},*/
369 /*{.addr = 0x00413810, .prod = 0x0000c242, .disable = 0x00000000},*/
370 /*{.addr = 0x00413a80, .prod = 0x0000c242, .disable = 0x00000000},*/
371 /*{.addr = 0x004139a8, .prod = 0x0000c242, .disable = 0x00000000},*/
372 /*{.addr = 0x00413c10, .prod = 0x0000c242, .disable = 0x00000000},*/
373 /*{.addr = 0x00413e80, .prod = 0x0000c242, .disable = 0x00000000},*/
374 /*{.addr = 0x00413da8, .prod = 0x0000c242, .disable = 0x00000000},*/
375 {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
376 {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
377 {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
378};
379
380/* blcg ltc */
381static const struct gating_desc gv100_blcg_ltc[] = {
382 {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000},
383 {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000},
384 {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000},
385 {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000},
386 {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000},
387 {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000},
388 {.addr = 0x001549e0, .prod = 0x00000044, .disable = 0x00000000},
389 {.addr = 0x001549c8, .prod = 0x00000044, .disable = 0x00000000},
390 {.addr = 0x00154be0, .prod = 0x00000044, .disable = 0x00000000},
391 {.addr = 0x00154bc8, .prod = 0x00000044, .disable = 0x00000000},
392 {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000},
393 {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000},
394 {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000},
395 {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000},
396 {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000},
397 {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000},
398 {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000},
399 {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000},
400 {.addr = 0x001569e0, .prod = 0x00000044, .disable = 0x00000000},
401 {.addr = 0x001569c8, .prod = 0x00000044, .disable = 0x00000000},
402 {.addr = 0x00156be0, .prod = 0x00000044, .disable = 0x00000000},
403 {.addr = 0x00156bc8, .prod = 0x00000044, .disable = 0x00000000},
404 {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000},
405 {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000},
406 /* fix priv error */
407 /*{.addr = 0x00158030, .prod = 0x00000044, .disable = 0x00000000},*/
408 /*{.addr = 0x00158040, .prod = 0x00000044, .disable = 0x00000000},*/
409 /*{.addr = 0x001585e0, .prod = 0x00000044, .disable = 0x00000000},*/
410 /*{.addr = 0x001585c8, .prod = 0x00000044, .disable = 0x00000000},*/
411 /*{.addr = 0x001587e0, .prod = 0x00000044, .disable = 0x00000000},*/
412 /*{.addr = 0x001587c8, .prod = 0x00000044, .disable = 0x00000000},*/
413 /*{.addr = 0x001589e0, .prod = 0x00000044, .disable = 0x00000000},*/
414 /*{.addr = 0x001589c8, .prod = 0x00000044, .disable = 0x00000000},*/
415 /*{.addr = 0x00158be0, .prod = 0x00000044, .disable = 0x00000000},*/
416 /*{.addr = 0x00158bc8, .prod = 0x00000044, .disable = 0x00000000},*/
417 /*{.addr = 0x001583e0, .prod = 0x00000044, .disable = 0x00000000},*/
418 /*{.addr = 0x001583c8, .prod = 0x00000044, .disable = 0x00000000},*/
419 /*{.addr = 0x0015a030, .prod = 0x00000044, .disable = 0x00000000},*/
420 /*{.addr = 0x0015a040, .prod = 0x00000044, .disable = 0x00000000},*/
421 /*{.addr = 0x0015a5e0, .prod = 0x00000044, .disable = 0x00000000},*/
422 /*{.addr = 0x0015a5c8, .prod = 0x00000044, .disable = 0x00000000},*/
423 /*{.addr = 0x0015a7e0, .prod = 0x00000044, .disable = 0x00000000},*/
424 /*{.addr = 0x0015a7c8, .prod = 0x00000044, .disable = 0x00000000},*/
425 /*{.addr = 0x0015a9e0, .prod = 0x00000044, .disable = 0x00000000},*/
426 /*{.addr = 0x0015a9c8, .prod = 0x00000044, .disable = 0x00000000},*/
427 /*{.addr = 0x0015abe0, .prod = 0x00000044, .disable = 0x00000000},*/
428 /*{.addr = 0x0015abc8, .prod = 0x00000044, .disable = 0x00000000},*/
429 /*{.addr = 0x0015a3e0, .prod = 0x00000044, .disable = 0x00000000},*/
430 /*{.addr = 0x0015a3c8, .prod = 0x00000044, .disable = 0x00000000},*/
431 /*{.addr = 0x0015c030, .prod = 0x00000044, .disable = 0x00000000},*/
432 /*{.addr = 0x0015c040, .prod = 0x00000044, .disable = 0x00000000},*/
433 /*{.addr = 0x0015c5e0, .prod = 0x00000044, .disable = 0x00000000},*/
434 /*{.addr = 0x0015c5c8, .prod = 0x00000044, .disable = 0x00000000},*/
435 /*{.addr = 0x0015c7e0, .prod = 0x00000044, .disable = 0x00000000},*/
436 /*{.addr = 0x0015c7c8, .prod = 0x00000044, .disable = 0x00000000},*/
437 /*{.addr = 0x0015c9e0, .prod = 0x00000044, .disable = 0x00000000},*/
438 /*{.addr = 0x0015c9c8, .prod = 0x00000044, .disable = 0x00000000},*/
439 /*{.addr = 0x0015cbe0, .prod = 0x00000044, .disable = 0x00000000},*/
440 /*{.addr = 0x0015cbc8, .prod = 0x00000044, .disable = 0x00000000},*/
441 /*{.addr = 0x0015c3e0, .prod = 0x00000044, .disable = 0x00000000},*/
442 /*{.addr = 0x0015c3c8, .prod = 0x00000044, .disable = 0x00000000},*/
443 /*{.addr = 0x0015e030, .prod = 0x00000044, .disable = 0x00000000},*/
444 /*{.addr = 0x0015e040, .prod = 0x00000044, .disable = 0x00000000},*/
445 /*{.addr = 0x0015e5e0, .prod = 0x00000044, .disable = 0x00000000},*/
446 /*{.addr = 0x0015e5c8, .prod = 0x00000044, .disable = 0x00000000},*/
447 /*{.addr = 0x0015e7e0, .prod = 0x00000044, .disable = 0x00000000},*/
448 /*{.addr = 0x0015e7c8, .prod = 0x00000044, .disable = 0x00000000},*/
449 /*{.addr = 0x0015e9e0, .prod = 0x00000044, .disable = 0x00000000},*/
450 /*{.addr = 0x0015e9c8, .prod = 0x00000044, .disable = 0x00000000},*/
451 /*{.addr = 0x0015ebe0, .prod = 0x00000044, .disable = 0x00000000},*/
452 /*{.addr = 0x0015ebc8, .prod = 0x00000044, .disable = 0x00000000},*/
453 /*{.addr = 0x0015e3e0, .prod = 0x00000044, .disable = 0x00000000},*/
454 /*{.addr = 0x0015e3c8, .prod = 0x00000044, .disable = 0x00000000},*/
455 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
456 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
457 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
458 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
459};
460
461/* blcg pwr_csb */
462static const struct gating_desc gv100_blcg_pwr_csb[] = {
463 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
464};
465
466/* blcg pmu */
467static const struct gating_desc gv100_blcg_pmu[] = {
468 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
469};
470
471/* blcg Xbar */
472static const struct gating_desc gv100_blcg_xbar[] = {
473 {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000},
474 {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000},
475 {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000},
476 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
477 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
478 {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000},
479 {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000},
480 {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000},
481 {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000},
482 {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000},
483};
484
485/* pg gr */
486static const struct gating_desc gv100_pg_gr[] = {
487};
488
489/* inline functions */
490void gv100_slcg_bus_load_gating_prod(struct gk20a *g,
491 bool prod)
492{
493 u32 i;
494 u32 size = sizeof(gv100_slcg_bus) / sizeof(struct gating_desc);
495
496 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
497 return;
498
499 for (i = 0; i < size; i++) {
500 if (prod)
501 gk20a_writel(g, gv100_slcg_bus[i].addr,
502 gv100_slcg_bus[i].prod);
503 else
504 gk20a_writel(g, gv100_slcg_bus[i].addr,
505 gv100_slcg_bus[i].disable);
506 }
507}
508
509void gv100_slcg_ce2_load_gating_prod(struct gk20a *g,
510 bool prod)
511{
512 u32 i;
513 u32 size = sizeof(gv100_slcg_ce2) / sizeof(struct gating_desc);
514
515 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
516 return;
517
518 for (i = 0; i < size; i++) {
519 if (prod)
520 gk20a_writel(g, gv100_slcg_ce2[i].addr,
521 gv100_slcg_ce2[i].prod);
522 else
523 gk20a_writel(g, gv100_slcg_ce2[i].addr,
524 gv100_slcg_ce2[i].disable);
525 }
526}
527
528void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g,
529 bool prod)
530{
531 u32 i;
532 u32 size = sizeof(gv100_slcg_chiplet) / sizeof(struct gating_desc);
533
534 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
535 return;
536
537 for (i = 0; i < size; i++) {
538 if (prod)
539 gk20a_writel(g, gv100_slcg_chiplet[i].addr,
540 gv100_slcg_chiplet[i].prod);
541 else
542 gk20a_writel(g, gv100_slcg_chiplet[i].addr,
543 gv100_slcg_chiplet[i].disable);
544 }
545}
546
547void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
548 bool prod)
549{
550}
551
552void gv100_slcg_fb_load_gating_prod(struct gk20a *g,
553 bool prod)
554{
555 u32 i;
556 u32 size = sizeof(gv100_slcg_fb) / sizeof(struct gating_desc);
557
558 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
559 return;
560
561 for (i = 0; i < size; i++) {
562 if (prod)
563 gk20a_writel(g, gv100_slcg_fb[i].addr,
564 gv100_slcg_fb[i].prod);
565 else
566 gk20a_writel(g, gv100_slcg_fb[i].addr,
567 gv100_slcg_fb[i].disable);
568 }
569}
570
571void gv100_slcg_fifo_load_gating_prod(struct gk20a *g,
572 bool prod)
573{
574 u32 i;
575 u32 size = sizeof(gv100_slcg_fifo) / sizeof(struct gating_desc);
576
577 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
578 return;
579
580 for (i = 0; i < size; i++) {
581 if (prod)
582 gk20a_writel(g, gv100_slcg_fifo[i].addr,
583 gv100_slcg_fifo[i].prod);
584 else
585 gk20a_writel(g, gv100_slcg_fifo[i].addr,
586 gv100_slcg_fifo[i].disable);
587 }
588}
589
590void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g,
591 bool prod)
592{
593 u32 i;
594 u32 size = sizeof(gv100_slcg_gr) / sizeof(struct gating_desc);
595
596 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
597 return;
598
599 for (i = 0; i < size; i++) {
600 if (prod)
601 gk20a_writel(g, gv100_slcg_gr[i].addr,
602 gv100_slcg_gr[i].prod);
603 else
604 gk20a_writel(g, gv100_slcg_gr[i].addr,
605 gv100_slcg_gr[i].disable);
606 }
607}
608
609void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g,
610 bool prod)
611{
612 u32 i;
613 u32 size = sizeof(gv100_slcg_ltc) / sizeof(struct gating_desc);
614
615 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
616 return;
617
618 for (i = 0; i < size; i++) {
619 if (prod)
620 gk20a_writel(g, gv100_slcg_ltc[i].addr,
621 gv100_slcg_ltc[i].prod);
622 else
623 gk20a_writel(g, gv100_slcg_ltc[i].addr,
624 gv100_slcg_ltc[i].disable);
625 }
626}
627
628void gv100_slcg_perf_load_gating_prod(struct gk20a *g,
629 bool prod)
630{
631 u32 i;
632 u32 size = sizeof(gv100_slcg_perf) / sizeof(struct gating_desc);
633
634 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
635 return;
636
637 for (i = 0; i < size; i++) {
638 if (prod)
639 gk20a_writel(g, gv100_slcg_perf[i].addr,
640 gv100_slcg_perf[i].prod);
641 else
642 gk20a_writel(g, gv100_slcg_perf[i].addr,
643 gv100_slcg_perf[i].disable);
644 }
645}
646
647void gv100_slcg_priring_load_gating_prod(struct gk20a *g,
648 bool prod)
649{
650 u32 i;
651 u32 size = sizeof(gv100_slcg_priring) / sizeof(struct gating_desc);
652
653 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
654 return;
655
656 for (i = 0; i < size; i++) {
657 if (prod)
658 gk20a_writel(g, gv100_slcg_priring[i].addr,
659 gv100_slcg_priring[i].prod);
660 else
661 gk20a_writel(g, gv100_slcg_priring[i].addr,
662 gv100_slcg_priring[i].disable);
663 }
664}
665
666void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
667 bool prod)
668{
669 u32 i;
670 u32 size = sizeof(gv100_slcg_pwr_csb) / sizeof(struct gating_desc);
671
672 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
673 return;
674
675 for (i = 0; i < size; i++) {
676 if (prod)
677 gk20a_writel(g, gv100_slcg_pwr_csb[i].addr,
678 gv100_slcg_pwr_csb[i].prod);
679 else
680 gk20a_writel(g, gv100_slcg_pwr_csb[i].addr,
681 gv100_slcg_pwr_csb[i].disable);
682 }
683}
684
685void gv100_slcg_pmu_load_gating_prod(struct gk20a *g,
686 bool prod)
687{
688 u32 i;
689 u32 size = sizeof(gv100_slcg_pmu) / sizeof(struct gating_desc);
690
691 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
692 return;
693
694 for (i = 0; i < size; i++) {
695 if (prod)
696 gk20a_writel(g, gv100_slcg_pmu[i].addr,
697 gv100_slcg_pmu[i].prod);
698 else
699 gk20a_writel(g, gv100_slcg_pmu[i].addr,
700 gv100_slcg_pmu[i].disable);
701 }
702}
703
704void gv100_slcg_therm_load_gating_prod(struct gk20a *g,
705 bool prod)
706{
707 u32 i;
708 u32 size = sizeof(gv100_slcg_therm) / sizeof(struct gating_desc);
709
710 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
711 return;
712
713 for (i = 0; i < size; i++) {
714 if (prod)
715 gk20a_writel(g, gv100_slcg_therm[i].addr,
716 gv100_slcg_therm[i].prod);
717 else
718 gk20a_writel(g, gv100_slcg_therm[i].addr,
719 gv100_slcg_therm[i].disable);
720 }
721}
722
723void gv100_slcg_xbar_load_gating_prod(struct gk20a *g,
724 bool prod)
725{
726 u32 i;
727 u32 size = sizeof(gv100_slcg_xbar) / sizeof(struct gating_desc);
728
729 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
730 return;
731
732 for (i = 0; i < size; i++) {
733 if (prod)
734 gk20a_writel(g, gv100_slcg_xbar[i].addr,
735 gv100_slcg_xbar[i].prod);
736 else
737 gk20a_writel(g, gv100_slcg_xbar[i].addr,
738 gv100_slcg_xbar[i].disable);
739 }
740}
741
742void gv100_blcg_bus_load_gating_prod(struct gk20a *g,
743 bool prod)
744{
745 u32 i;
746 u32 size = sizeof(gv100_blcg_bus) / sizeof(struct gating_desc);
747
748 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
749 return;
750
751 for (i = 0; i < size; i++) {
752 if (prod)
753 gk20a_writel(g, gv100_blcg_bus[i].addr,
754 gv100_blcg_bus[i].prod);
755 else
756 gk20a_writel(g, gv100_blcg_bus[i].addr,
757 gv100_blcg_bus[i].disable);
758 }
759}
760
761void gv100_blcg_ce_load_gating_prod(struct gk20a *g,
762 bool prod)
763{
764 u32 i;
765 u32 size = sizeof(gv100_blcg_ce) / sizeof(struct gating_desc);
766
767 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
768 return;
769
770 for (i = 0; i < size; i++) {
771 if (prod)
772 gk20a_writel(g, gv100_blcg_ce[i].addr,
773 gv100_blcg_ce[i].prod);
774 else
775 gk20a_writel(g, gv100_blcg_ce[i].addr,
776 gv100_blcg_ce[i].disable);
777 }
778}
779
780void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
781 bool prod)
782{
783 u32 i;
784 u32 size = sizeof(gv100_blcg_ctxsw_prog) / sizeof(struct gating_desc);
785
786 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
787 return;
788
789 for (i = 0; i < size; i++) {
790 if (prod)
791 gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr,
792 gv100_blcg_ctxsw_prog[i].prod);
793 else
794 gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr,
795 gv100_blcg_ctxsw_prog[i].disable);
796 }
797}
798
799void gv100_blcg_fb_load_gating_prod(struct gk20a *g,
800 bool prod)
801{
802 u32 i;
803 u32 size = sizeof(gv100_blcg_fb) / sizeof(struct gating_desc);
804
805 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
806 return;
807
808 for (i = 0; i < size; i++) {
809 if (prod)
810 gk20a_writel(g, gv100_blcg_fb[i].addr,
811 gv100_blcg_fb[i].prod);
812 else
813 gk20a_writel(g, gv100_blcg_fb[i].addr,
814 gv100_blcg_fb[i].disable);
815 }
816}
817
818void gv100_blcg_fifo_load_gating_prod(struct gk20a *g,
819 bool prod)
820{
821 u32 i;
822 u32 size = sizeof(gv100_blcg_fifo) / sizeof(struct gating_desc);
823
824 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
825 return;
826
827 for (i = 0; i < size; i++) {
828 if (prod)
829 gk20a_writel(g, gv100_blcg_fifo[i].addr,
830 gv100_blcg_fifo[i].prod);
831 else
832 gk20a_writel(g, gv100_blcg_fifo[i].addr,
833 gv100_blcg_fifo[i].disable);
834 }
835}
836
837void gv100_blcg_gr_load_gating_prod(struct gk20a *g,
838 bool prod)
839{
840 u32 i;
841 u32 size = sizeof(gv100_blcg_gr) / sizeof(struct gating_desc);
842
843 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
844 return;
845
846 for (i = 0; i < size; i++) {
847 if (prod)
848 gk20a_writel(g, gv100_blcg_gr[i].addr,
849 gv100_blcg_gr[i].prod);
850 else
851 gk20a_writel(g, gv100_blcg_gr[i].addr,
852 gv100_blcg_gr[i].disable);
853 }
854}
855
856void gv100_blcg_ltc_load_gating_prod(struct gk20a *g,
857 bool prod)
858{
859 u32 i;
860 u32 size = sizeof(gv100_blcg_ltc) / sizeof(struct gating_desc);
861
862 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
863 return;
864
865 for (i = 0; i < size; i++) {
866 if (prod)
867 gk20a_writel(g, gv100_blcg_ltc[i].addr,
868 gv100_blcg_ltc[i].prod);
869 else
870 gk20a_writel(g, gv100_blcg_ltc[i].addr,
871 gv100_blcg_ltc[i].disable);
872 }
873}
874
875void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
876 bool prod)
877{
878 u32 i;
879 u32 size = sizeof(gv100_blcg_pwr_csb) / sizeof(struct gating_desc);
880
881 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
882 return;
883
884 for (i = 0; i < size; i++) {
885 if (prod)
886 gk20a_writel(g, gv100_blcg_pwr_csb[i].addr,
887 gv100_blcg_pwr_csb[i].prod);
888 else
889 gk20a_writel(g, gv100_blcg_pwr_csb[i].addr,
890 gv100_blcg_pwr_csb[i].disable);
891 }
892}
893
894void gv100_blcg_pmu_load_gating_prod(struct gk20a *g,
895 bool prod)
896{
897 u32 i;
898 u32 size = sizeof(gv100_blcg_pmu) / sizeof(struct gating_desc);
899
900 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
901 return;
902
903 for (i = 0; i < size; i++) {
904 if (prod)
905 gk20a_writel(g, gv100_blcg_pmu[i].addr,
906 gv100_blcg_pmu[i].prod);
907 else
908 gk20a_writel(g, gv100_blcg_pmu[i].addr,
909 gv100_blcg_pmu[i].disable);
910 }
911}
912
913void gv100_blcg_xbar_load_gating_prod(struct gk20a *g,
914 bool prod)
915{
916 u32 i;
917 u32 size = sizeof(gv100_blcg_xbar) / sizeof(struct gating_desc);
918
919 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
920 return;
921
922 for (i = 0; i < size; i++) {
923 if (prod)
924 gk20a_writel(g, gv100_blcg_xbar[i].addr,
925 gv100_blcg_xbar[i].prod);
926 else
927 gk20a_writel(g, gv100_blcg_xbar[i].addr,
928 gv100_blcg_xbar[i].disable);
929 }
930}
931
932void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g,
933 bool prod)
934{
935 u32 i;
936 u32 size = sizeof(gv100_pg_gr) / sizeof(struct gating_desc);
937
938 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
939 return;
940
941 for (i = 0; i < size; i++) {
942 if (prod)
943 gk20a_writel(g, gv100_pg_gr[i].addr,
944 gv100_pg_gr[i].prod);
945 else
946 gk20a_writel(g, gv100_pg_gr[i].addr,
947 gv100_pg_gr[i].disable);
948 }
949}
950
951#endif /* __gv100_gating_reglist_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 13:24:47 -0400