gpu: nvgpu: gv100: fix num_fbpas while adding ctxsw buffer entries

For LIST_nv_pm_fbpa_ctx_regs, we right now call
add_ctxsw_buffer_map_entries_subunits() to add registers corresponding
to all the FBPAs

But while configuring total number of registers, we do not consider
floorswept FBPAs and that causes misalignment in subsequent lists for GV100

Fix this by reading disabled/floorswept FBPAs from fuse and consider only those
FBPAs which are active for GV100

Add new HAL (*add_ctxsw_reg_pm_fbpa) to support this setting and define a
common HAL gr_gk20a_add_ctxsw_reg_pm_fbpa() for all chips except GV100

Define GV100 specific gr_gv100_add_ctxsw_reg_pm_fbpa() with above mentioned
implementation to consider floorsweeping

Bug 1998067

Change-Id: Id560551bb0b8142791c117b6d27864566c90b489
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676654
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 44 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c
index bf143dbb..3aed7a19 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c
@@ -34,6 +34,8 @@
 
 #include <nvgpu/hw/gv100/hw_gr_gv100.h>
 #include <nvgpu/hw/gv100/hw_proj_gv100.h>
+#include <nvgpu/hw/gv100/hw_fuse_gv100.h>
+
 
 /*
  *  Estimate performance if the given logical TPC in the given logical GPC were
@@ -329,3 +331,45 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g)
 
         return size;
 }
+
+int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g,
+                                struct ctxsw_buf_offset_map_entry *map,
+                                struct aiv_list_gk20a *regs,
+                                u32 *count, u32 *offset,
+                                u32 max_cnt, u32 base,
+                                u32 num_fbpas, u32 stride, u32 mask)
+{
+        u32 fbpa_id;
+        u32 idx;
+        u32 cnt = *count;
+        u32 off = *offset;
+        u32 active_fbpa_mask;
+
+        if ((cnt + (regs->count * num_fbpas)) > max_cnt)
+                return -EINVAL;
+
+        /*
+         * Read active fbpa mask from fuse
+         * Note that 0:enable and 1:disable in value read from fuse so we've to
+         * flip the bits.
+         * Also set unused bits to zero
+         */
+        active_fbpa_mask = nvgpu_readl(g, fuse_status_opt_fbio_r());
+        active_fbpa_mask = ~active_fbpa_mask;
+        active_fbpa_mask = active_fbpa_mask & ((1 << num_fbpas) - 1);
+
+        for (idx = 0; idx < regs->count; idx++) {
+                for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) {
+                        if (active_fbpa_mask & BIT(fbpa_id)) {
+                                map[cnt].addr = base +
+                                                (regs->l[idx].addr & mask) +
+                                                (fbpa_id * stride);
+                                map[cnt++].offset = off;
+                                off += 4;
+                        }
+                }
+        }
+        *count = cnt;
+        *offset = off;
+        return 0;
+}