diff options
author | smadhavan <smadhavan@nvidia.com> | 2018-09-11 01:59:00 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-14 02:45:26 -0400 |
commit | 0ece054d13a67ab01a1074bd7f06f941593251dc (patch) | |
tree | 57e0c485da65eecb7de13ae9fdcebdb88c41973d /drivers/gpu/nvgpu/gv100/flcn_gv100.h | |
parent | a605a09e2a74f31abc3755a6e383311317e3b909 (diff) |
nvgpu: gv100: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gv100 by renaming
them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when
there is no keyword repetition between file name and directory or
'NVGPU_HEADER-NAME' when there is repetition.
JIRA NVGPU-1028
Change-Id: I0e4fabc8b31d0bfd66ab541435ac8813e5cc4c1d
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1815554
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv100/flcn_gv100.h')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/flcn_gv100.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv100/flcn_gv100.h b/drivers/gpu/nvgpu/gv100/flcn_gv100.h index 9207519a..f3116058 100644 --- a/drivers/gpu/nvgpu/gv100/flcn_gv100.h +++ b/drivers/gpu/nvgpu/gv100/flcn_gv100.h | |||
@@ -19,9 +19,9 @@ | |||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | #ifndef __FLCN_GV100_H__ | 22 | #ifndef NVGPU_FLCN_GV100_H |
23 | #define __FLCN_GV100_H__ | 23 | #define NVGPU_FLCN_GV100_H |
24 | 24 | ||
25 | int gv100_falcon_hal_sw_init(struct nvgpu_falcon *flcn); | 25 | int gv100_falcon_hal_sw_init(struct nvgpu_falcon *flcn); |
26 | 26 | ||
27 | #endif /* __FLCN_GV100_H__ */ | 27 | #endif /* NVGPU_FLCN_GV100_H */ |