diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-10-27 05:06:59 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:54 -0400 |
commit | 2d5ff668cbc6a932df2c9cf79627d1d340e5c2c0 (patch) | |
tree | 1d9bc4b774a9c2cea339891eaef3af5b87ee354d /drivers/gpu/nvgpu/gr_ops.h | |
parent | 23a182aaa61d120c965f1bce09609cc14d4e14eb (diff) |
gpu: nvgpu: GR and LTC HAL to use const structs
Convert GR and LTC HALs to use const structs, and initialize them
with macros.
Bug 1567274
Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590371
Diffstat (limited to 'drivers/gpu/nvgpu/gr_ops.h')
-rw-r--r-- | drivers/gpu/nvgpu/gr_ops.h | 103 |
1 files changed, 103 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gr_ops.h b/drivers/gpu/nvgpu/gr_ops.h new file mode 100644 index 00000000..bb2d47fa --- /dev/null +++ b/drivers/gpu/nvgpu/gr_ops.h | |||
@@ -0,0 +1,103 @@ | |||
1 | #ifndef _NVGPU_GR_OPS_H_ | ||
2 | #define _NVGPU_GR_OPS_H_ | ||
3 | |||
4 | #include <linux/types.h> | ||
5 | #include <linux/printk.h> | ||
6 | |||
7 | /* TBD: rename these. s/gk20a/nvgpu/g s/gpu/nvgpu/g*/ | ||
8 | struct gk20a; | ||
9 | struct channel_ctx_gk20a; | ||
10 | struct channel_gk20a; | ||
11 | struct gr_gk20a; | ||
12 | struct gk20a_ctxsw_ucode_segments; | ||
13 | struct nvgpu_alloc_obj_ctx_args; | ||
14 | struct nvgpu_free_obj_ctx_args; | ||
15 | struct gr_zcull_info; | ||
16 | |||
17 | typedef int (*gr_init_fs_state_fn)(struct gk20a *g); | ||
18 | typedef void (*gr_access_smpc_reg_fn)(struct gk20a *g, u32 quad, u32 offset); | ||
19 | typedef void (*gr_bundle_cb_defaults_fn)(struct gk20a *g); | ||
20 | typedef void (*gr_cb_size_default_fn)(struct gk20a *g); | ||
21 | typedef int (*gr_calc_global_ctx_buffer_size_fn)(struct gk20a *g); | ||
22 | typedef void (*gr_commit_global_attrib_cb_fn)(struct gk20a *g, | ||
23 | struct channel_ctx_gk20a *ch_ctx, | ||
24 | u64 addr, bool patch); | ||
25 | typedef void (*gr_commit_global_bundle_cb_fn)(struct gk20a *g, | ||
26 | struct channel_ctx_gk20a *ch_ctx, | ||
27 | u64 addr, u64 size, bool patch); | ||
28 | typedef int (*gr_commit_global_cb_manager_fn)(struct gk20a *g, | ||
29 | struct channel_gk20a *ch, | ||
30 | bool patch); | ||
31 | typedef void (*gr_commit_global_pagepool_fn)(struct gk20a *g, | ||
32 | struct channel_ctx_gk20a *ch_ctx, | ||
33 | u64 addr, u32 size, bool patch); | ||
34 | typedef void (*gr_init_gpc_mmu_fn)(struct gk20a *g); | ||
35 | typedef int (*gr_handle_sw_method_fn)(struct gk20a *g, u32 addr, | ||
36 | u32 class_num, u32 offset, u32 data); | ||
37 | typedef void (*gr_set_alpha_circular_buffer_size_fn)(struct gk20a *g, | ||
38 | u32 data); | ||
39 | typedef void (*gr_set_circular_buffer_size_fn)(struct gk20a *g, u32 data); | ||
40 | typedef void (*gr_enable_hww_exceptions_fn)(struct gk20a *g); | ||
41 | typedef bool (*gr_is_valid_class_fn)(struct gk20a *g, u32 class_num); | ||
42 | typedef void (*gr_get_sm_dsm_perf_regs_fn)(struct gk20a *g, | ||
43 | u32 *num_sm_dsm_perf_regs, | ||
44 | u32 **sm_dsm_perf_regs, | ||
45 | u32 *perf_register_stride); | ||
46 | typedef void (*gr_get_sm_dsm_perf_ctrl_regs_fn)(struct gk20a *g, | ||
47 | u32 *num_sm_dsm_perf_regs, | ||
48 | u32 **sm_dsm_perf_regs, | ||
49 | u32 *perf_register_stride); | ||
50 | typedef void (*gr_set_hww_esr_report_mask_fn)(struct gk20a *g); | ||
51 | typedef int (*gr_setup_alpha_beta_tables_fn)(struct gk20a *g, | ||
52 | struct gr_gk20a *gr); | ||
53 | typedef int (*gr_falcon_load_ucode_fn)(struct gk20a *g, | ||
54 | u64 addr_base, | ||
55 | struct gk20a_ctxsw_ucode_segments *segments, | ||
56 | u32 reg_offset); | ||
57 | typedef int (*gr_load_ctxsw_ucode_fn)(struct gk20a *g); | ||
58 | typedef u32 (*gr_get_gpc_tpc_mask_fn)(struct gk20a *g, u32 gpc_index); | ||
59 | typedef void (*gr_free_channel_ctx_fn)(struct channel_gk20a *c); | ||
60 | typedef int (*gr_alloc_obj_ctx_fn)(struct channel_gk20a *c, | ||
61 | struct nvgpu_alloc_obj_ctx_args *args); | ||
62 | typedef int (*gr_free_obj_ctx_fn)(struct channel_gk20a *c, | ||
63 | struct nvgpu_free_obj_ctx_args *args); | ||
64 | typedef int (*gr_bind_ctxsw_zcull_fn)(struct gk20a *g, struct gr_gk20a *gr, | ||
65 | struct channel_gk20a *c, u64 zcull_va, | ||
66 | u32 mode); | ||
67 | typedef int (*gr_get_zcull_info_fn)(struct gk20a *g, struct gr_gk20a *gr, | ||
68 | struct gr_zcull_info *zcull_params); | ||
69 | |||
70 | #define __op_decl(X) gr_##X##_fn X | ||
71 | |||
72 | struct gpu_gr_ops { | ||
73 | __op_decl(init_fs_state); | ||
74 | __op_decl(access_smpc_reg); | ||
75 | __op_decl(bundle_cb_defaults); | ||
76 | __op_decl(cb_size_default); | ||
77 | __op_decl(calc_global_ctx_buffer_size); | ||
78 | __op_decl(commit_global_attrib_cb); | ||
79 | __op_decl(commit_global_bundle_cb); | ||
80 | __op_decl(commit_global_cb_manager); | ||
81 | __op_decl(commit_global_pagepool); | ||
82 | __op_decl(init_gpc_mmu); | ||
83 | __op_decl(handle_sw_method); | ||
84 | __op_decl(set_alpha_circular_buffer_size); | ||
85 | __op_decl(set_circular_buffer_size); | ||
86 | __op_decl(enable_hww_exceptions); | ||
87 | __op_decl(is_valid_class); | ||
88 | __op_decl(get_sm_dsm_perf_regs); | ||
89 | __op_decl(get_sm_dsm_perf_ctrl_regs); | ||
90 | __op_decl(set_hww_esr_report_mask); | ||
91 | __op_decl(setup_alpha_beta_tables); | ||
92 | __op_decl(falcon_load_ucode); | ||
93 | __op_decl(load_ctxsw_ucode); | ||
94 | __op_decl(get_gpc_tpc_mask); | ||
95 | __op_decl(free_channel_ctx); | ||
96 | __op_decl(alloc_obj_ctx); | ||
97 | __op_decl(free_obj_ctx); | ||
98 | __op_decl(bind_ctxsw_zcull); | ||
99 | __op_decl(get_zcull_info); | ||
100 | }; | ||
101 | #undef __op_decl | ||
102 | |||
103 | #endif | ||