diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-11-09 18:32:11 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-22 03:59:18 -0500 |
commit | f34a4d0b125ebf45373e40478925b3eb75b7898a (patch) | |
tree | a6bac09ad2f4c38289048acefd724ff2bd3c279f /drivers/gpu/nvgpu/gp10b | |
parent | f53a0dd96b25cfb64b17ab816ae1f9b0b144db07 (diff) |
gpu: nvgpu: CONFIG_TEGRA_ACR is supported by default
TEGRA_ACR config is supposed to be enabled maxwell
onwards. Since gk20a support is no longer supported,
delete code that is not under TEGRA_ACR config
Change-Id: Id52485680bca1ceaadcb94f9603c0898c2002e02
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595437
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 9b3d1a2c..0b2a5712 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -662,7 +662,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
662 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 662 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
663 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 663 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
664 | 664 | ||
665 | #ifdef CONFIG_TEGRA_ACR | ||
666 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 665 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
667 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | 666 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
668 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 667 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
@@ -680,24 +679,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
680 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 679 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
681 | } | 680 | } |
682 | } | 681 | } |
683 | #else | ||
684 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
685 | gk20a_dbg_info("running simulator with PRIV security disabled"); | ||
686 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
687 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
688 | } else { | ||
689 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
690 | if (val) { | ||
691 | gk20a_dbg_info("priv security is not supported but enabled"); | ||
692 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
693 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
694 | return -EPERM; | ||
695 | } else { | ||
696 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
697 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
698 | } | ||
699 | } | ||
700 | #endif | ||
701 | 682 | ||
702 | /* priv security dependent ops */ | 683 | /* priv security dependent ops */ |
703 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 684 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |