diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-12-15 13:25:22 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-12-28 13:01:32 -0500 |
commit | f19f22fcc8ef21b363b873c499cbd2e690af29f8 (patch) | |
tree | 02d6b8280af305d0339ed860e331ab091d4b49d2 /drivers/gpu/nvgpu/gp10b | |
parent | aa52601f620423fdd98b79e2c2c5e1d767a5f685 (diff) |
gpu: nvgpu: Remove support for channel events
Remove support for events for bare channels. All users have already
moved to TSGs and TSG events.
Bug 1842197
Change-Id: Ib3ff68134ad9515ee761d0f0e19a3150a0b744ab
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1618906
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 3b63626c..b5194223 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1709,6 +1709,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1709 | { | 1709 | { |
1710 | int ret; | 1710 | int ret; |
1711 | struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; | 1711 | struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; |
1712 | struct tsg_gk20a *tsg; | ||
1712 | 1713 | ||
1713 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); | 1714 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); |
1714 | 1715 | ||
@@ -1773,15 +1774,10 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1773 | gr_ctx->cilp_preempt_pending = true; | 1774 | gr_ctx->cilp_preempt_pending = true; |
1774 | g->gr.cilp_preempt_pending_chid = fault_ch->chid; | 1775 | g->gr.cilp_preempt_pending_chid = fault_ch->chid; |
1775 | 1776 | ||
1776 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { | 1777 | tsg = &g->fifo.tsg[fault_ch->tsgid]; |
1777 | struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; | ||
1778 | 1778 | ||
1779 | gk20a_tsg_event_id_post_event(tsg, | 1779 | gk20a_tsg_event_id_post_event(tsg, |
1780 | NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED); | 1780 | NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED); |
1781 | } else { | ||
1782 | gk20a_channel_event_id_post_event(fault_ch, | ||
1783 | NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED); | ||
1784 | } | ||
1785 | 1781 | ||
1786 | return 0; | 1782 | return 0; |
1787 | } | 1783 | } |
@@ -1948,6 +1944,7 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g, | |||
1948 | struct channel_gk20a *ch; | 1944 | struct channel_gk20a *ch; |
1949 | int chid = -1; | 1945 | int chid = -1; |
1950 | int ret = 0; | 1946 | int ret = 0; |
1947 | struct tsg_gk20a *tsg; | ||
1951 | 1948 | ||
1952 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); | 1949 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); |
1953 | 1950 | ||
@@ -1984,15 +1981,10 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g, | |||
1984 | /* Post events to UMD */ | 1981 | /* Post events to UMD */ |
1985 | gk20a_dbg_gpu_post_events(ch); | 1982 | gk20a_dbg_gpu_post_events(ch); |
1986 | 1983 | ||
1987 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 1984 | tsg = &g->fifo.tsg[ch->tsgid]; |
1988 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | ||
1989 | 1985 | ||
1990 | gk20a_tsg_event_id_post_event(tsg, | 1986 | gk20a_tsg_event_id_post_event(tsg, |
1991 | NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE); | 1987 | NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE); |
1992 | } else { | ||
1993 | gk20a_channel_event_id_post_event(ch, | ||
1994 | NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE); | ||
1995 | } | ||
1996 | 1988 | ||
1997 | gk20a_channel_put(ch); | 1989 | gk20a_channel_put(ch); |
1998 | } | 1990 | } |