diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-08-16 19:19:53 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-04 05:21:47 -0400 |
commit | edb116661348f1bc843849cdcc318fa47cf9724a (patch) | |
tree | 61d978a3518a51bdb82e2d3681abf5fc9c75821e /drivers/gpu/nvgpu/gp10b | |
parent | 2559fa295d0c478466e47496174fa2108ab01c33 (diff) |
gpu: nvgpu: rename ops.mm.get_physical_addr_bits
Rename get_physical_addr_bits and related functions to something that
more clearly conveys what they are doing. The basic idea of these
functions is to translate from a physical GPU address to a IOMMU GPU
address. To do that a particular bit (that varies from chip to chip)
is added to the physical address.
JIRA NVGPU-68
Change-Id: I536cc595c4397aad69a24f740bc74db03f52bc0a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1542966
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index e64bb9cc..0db6b3f7 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -478,7 +478,7 @@ static const struct gpu_ops gp10b_ops = { | |||
478 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | 478 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, |
479 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | 479 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, |
480 | .gpu_phys_addr = gm20b_gpu_phys_addr, | 480 | .gpu_phys_addr = gm20b_gpu_phys_addr, |
481 | .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, | 481 | .get_iommu_bit = gp10b_mm_get_iommu_bit, |
482 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | 482 | .get_mmu_levels = gp10b_mm_get_mmu_levels, |
483 | .init_pdb = gp10b_mm_init_pdb, | 483 | .init_pdb = gp10b_mm_init_pdb, |
484 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, | 484 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 96da6cf5..06a9b929 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -41,7 +41,7 @@ u32 gp10b_mm_get_default_big_page_size(void) | |||
41 | return SZ_64K; | 41 | return SZ_64K; |
42 | } | 42 | } |
43 | 43 | ||
44 | u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) | 44 | u32 gp10b_mm_get_iommu_bit(struct gk20a *g) |
45 | { | 45 | { |
46 | return 36; | 46 | return 36; |
47 | } | 47 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index ab59069e..b6bcb04a 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h | |||
@@ -29,7 +29,7 @@ struct nvgpu_mem; | |||
29 | struct vm_gk20a; | 29 | struct vm_gk20a; |
30 | 30 | ||
31 | u32 gp10b_mm_get_default_big_page_size(void); | 31 | u32 gp10b_mm_get_default_big_page_size(void); |
32 | u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g); | 32 | u32 gp10b_mm_get_iommu_bit(struct gk20a *g); |
33 | int gp10b_init_mm_setup_hw(struct gk20a *g); | 33 | int gp10b_init_mm_setup_hw(struct gk20a *g); |
34 | int gb10b_init_bar2_vm(struct gk20a *g); | 34 | int gb10b_init_bar2_vm(struct gk20a *g); |
35 | int gb10b_init_bar2_mm_hw_setup(struct gk20a *g); | 35 | int gb10b_init_bar2_mm_hw_setup(struct gk20a *g); |