gpu: nvgpu: Move isr related fields from gk20a

Move fields in struct gk20a related to interrupt handling into
Linux specific nvgpu_os_linux. At the same time move the counter
logic from function in HAL into Linux specific code, and two Linux
specific power management functions from generic gk20a.c to Linux
specific module.c.

JIRA NVGPU-123

Change-Id: I0a08fd2e81297c8dff7a85c263ded928496c4de0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1528177
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 0 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 718869f6..b7a52349 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -71,14 +71,12 @@ void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
 void mc_gp10b_isr_stall(struct gk20a *g)
 {
         u32 mc_intr_0;
-        int hw_irq_count;
 
         u32 engine_id_idx;
         u32 active_engine_id = 0;
         u32 engine_enum = ENGINE_INVAL_GK20A;
 
         mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
-        hw_irq_count = atomic_read(&g->hw_irq_stall_count);
 
         gk20a_dbg(gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0);
 
@@ -116,9 +114,6 @@ void mc_gp10b_isr_stall(struct gk20a *g)
         if (mc_intr_0 & mc_intr_pbus_pending_f())
                 g->ops.bus.isr(g);
 
-        /* sync handled irq counter before re-enabling interrupts */
-        atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
-
         gk20a_dbg(gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0);
 
 }