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authorVinod G <vinodg@nvidia.com>2018-05-17 17:43:51 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-21 16:55:00 -0400
commitdffeea5deb9754686e60eafec5194b7bf7bb4e77 (patch)
tree20c413a02da8da02ef45335941b142ea790dd2eb /drivers/gpu/nvgpu/gp10b
parentbd7489886c0198fb65f939e73ab5e067f09c51b4 (diff)
gpu: nvgpu: Code updates for MISRA violations
As part of the MISRA fixes, moving all the gating_reglist files to common/clock_gating dir, the new directory structure suggested to follow. Removed unused gating_reglist files for gk20a JIRA NVGPU-646 Change-Id: I388855befcf991ee68eeffed10fe9ac456210649 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722330 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c742
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h99
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c2
3 files changed, 1 insertions, 842 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c
deleted file mode 100644
index 4355f698..00000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c
+++ /dev/null
@@ -1,742 +0,0 @@
1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 *
22 * This file is autogenerated. Do not edit.
23 */
24
25#ifndef __gp10b_gating_reglist_h__
26#define __gp10b_gating_reglist_h__
27
28#include "gp10b_gating_reglist.h"
29#include <nvgpu/enabled.h>
30
31struct gating_desc {
32 u32 addr;
33 u32 prod;
34 u32 disable;
35};
36/* slcg bus */
37static const struct gating_desc gp10b_slcg_bus[] = {
38 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
39};
40
41/* slcg ce2 */
42static const struct gating_desc gp10b_slcg_ce2[] = {
43 {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
44};
45
46/* slcg chiplet */
47static const struct gating_desc gp10b_slcg_chiplet[] = {
48 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
49 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
50 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
51 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
52};
53
54/* slcg fb */
55static const struct gating_desc gp10b_slcg_fb[] = {
56 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
57 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
58};
59
60/* slcg fifo */
61static const struct gating_desc gp10b_slcg_fifo[] = {
62 {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe},
63};
64
65/* slcg gr */
66static const struct gating_desc gp10b_slcg_gr[] = {
67 {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe},
68 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
69 {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
70 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
71 {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe},
72 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
73 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
74 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
75 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
76 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
77 {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
78 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
79 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
80 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
81 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e},
82 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
83 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
84 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
85 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
86 {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe},
87 {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe},
88 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
89 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
90 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
91 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
92 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
93 {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
94 {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
95 {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
96 {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
97 {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
98 {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
99 {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
100 {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
101 {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
102 {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
103 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
104 {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
105 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
106 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
107 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
108 {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
109 {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
110 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
111 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
112 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
113 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
114 {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
115 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
116 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
117 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
118 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
119};
120
121/* slcg ltc */
122static const struct gating_desc gp10b_slcg_ltc[] = {
123 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
124 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
125};
126
127/* slcg perf */
128static const struct gating_desc gp10b_slcg_perf[] = {
129 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
130 {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
131 {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
132 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
133};
134
135/* slcg PriRing */
136static const struct gating_desc gp10b_slcg_priring[] = {
137 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
138};
139
140/* slcg pwr_csb */
141static const struct gating_desc gp10b_slcg_pwr_csb[] = {
142 {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe},
143 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
144 {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe},
145 {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f},
146};
147
148/* slcg pmu */
149static const struct gating_desc gp10b_slcg_pmu[] = {
150 {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
151 {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe},
152 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
153};
154
155/* therm gr */
156static const struct gating_desc gp10b_slcg_therm[] = {
157 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
158};
159
160/* slcg Xbar */
161static const struct gating_desc gp10b_slcg_xbar[] = {
162 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
163 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
164};
165
166/* blcg bus */
167static const struct gating_desc gp10b_blcg_bus[] = {
168 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
169};
170
171/* blcg ce */
172static const struct gating_desc gp10b_blcg_ce[] = {
173 {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000},
174};
175
176/* blcg ctxsw prog */
177static const struct gating_desc gp10b_blcg_ctxsw_prog[] = {
178};
179
180/* blcg fb */
181static const struct gating_desc gp10b_blcg_fb[] = {
182 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
183 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
184 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
185 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
186 {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
187};
188
189/* blcg fifo */
190static const struct gating_desc gp10b_blcg_fifo[] = {
191 {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
192};
193
194/* blcg gr */
195static const struct gating_desc gp10b_blcg_gr[] = {
196 {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
197 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
198 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
199 {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
200 {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
201 {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
202 {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
203 {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
204 {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
205 /* fix priv error */
206 /*{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},*/
207 {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
208 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
209 {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
210 {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
211 {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
212 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
213 {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
214 {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
215 {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
216 {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
217 {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
218 {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
219 {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
220 {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
221 {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
222 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
223 {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
224 {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
225 {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
226 {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
227 {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
228 {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
229 {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
230 {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
231 {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
232 {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
233 {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
234 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
235 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
236 {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
237 {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
238 {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
239 {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
240 {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
241 {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
242 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
243 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
244 {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
245 {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
246 {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
247 {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
248 {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
249 {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
250};
251
252/* blcg ltc */
253static const struct gating_desc gp10b_blcg_ltc[] = {
254 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
255 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
256 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
257 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
258};
259
260/* blcg pwr_csb */
261static const struct gating_desc gp10b_blcg_pwr_csb[] = {
262 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
263};
264
265/* blcg pmu */
266static const struct gating_desc gp10b_blcg_pmu[] = {
267 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
268};
269
270/* blcg Xbar */
271static const struct gating_desc gp10b_blcg_xbar[] = {
272 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
273 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
274};
275
276/* pg gr */
277static const struct gating_desc gp10b_pg_gr[] = {
278};
279
280/* inline functions */
281void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
282 bool prod)
283{
284 u32 i;
285 u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc);
286
287 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
288 return;
289
290 for (i = 0; i < size; i++) {
291 if (prod)
292 gk20a_writel(g, gp10b_slcg_bus[i].addr,
293 gp10b_slcg_bus[i].prod);
294 else
295 gk20a_writel(g, gp10b_slcg_bus[i].addr,
296 gp10b_slcg_bus[i].disable);
297 }
298}
299
300void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
301 bool prod)
302{
303 u32 i;
304 u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc);
305
306 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
307 return;
308
309 for (i = 0; i < size; i++) {
310 if (prod)
311 gk20a_writel(g, gp10b_slcg_ce2[i].addr,
312 gp10b_slcg_ce2[i].prod);
313 else
314 gk20a_writel(g, gp10b_slcg_ce2[i].addr,
315 gp10b_slcg_ce2[i].disable);
316 }
317}
318
319void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
320 bool prod)
321{
322 u32 i;
323 u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc);
324
325 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
326 return;
327
328 for (i = 0; i < size; i++) {
329 if (prod)
330 gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
331 gp10b_slcg_chiplet[i].prod);
332 else
333 gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
334 gp10b_slcg_chiplet[i].disable);
335 }
336}
337
338void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
339 bool prod)
340{
341}
342
343void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
344 bool prod)
345{
346 u32 i;
347 u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc);
348
349 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
350 return;
351
352 for (i = 0; i < size; i++) {
353 if (prod)
354 gk20a_writel(g, gp10b_slcg_fb[i].addr,
355 gp10b_slcg_fb[i].prod);
356 else
357 gk20a_writel(g, gp10b_slcg_fb[i].addr,
358 gp10b_slcg_fb[i].disable);
359 }
360}
361
362void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
363 bool prod)
364{
365 u32 i;
366 u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc);
367
368 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
369 return;
370
371 for (i = 0; i < size; i++) {
372 if (prod)
373 gk20a_writel(g, gp10b_slcg_fifo[i].addr,
374 gp10b_slcg_fifo[i].prod);
375 else
376 gk20a_writel(g, gp10b_slcg_fifo[i].addr,
377 gp10b_slcg_fifo[i].disable);
378 }
379}
380
381void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
382 bool prod)
383{
384 u32 i;
385 u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc);
386
387 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
388 return;
389
390 for (i = 0; i < size; i++) {
391 if (prod)
392 gk20a_writel(g, gp10b_slcg_gr[i].addr,
393 gp10b_slcg_gr[i].prod);
394 else
395 gk20a_writel(g, gp10b_slcg_gr[i].addr,
396 gp10b_slcg_gr[i].disable);
397 }
398}
399
400void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
401 bool prod)
402{
403 u32 i;
404 u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc);
405
406 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
407 return;
408
409 for (i = 0; i < size; i++) {
410 if (prod)
411 gk20a_writel(g, gp10b_slcg_ltc[i].addr,
412 gp10b_slcg_ltc[i].prod);
413 else
414 gk20a_writel(g, gp10b_slcg_ltc[i].addr,
415 gp10b_slcg_ltc[i].disable);
416 }
417}
418
419void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
420 bool prod)
421{
422 u32 i;
423 u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc);
424
425 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
426 return;
427
428 for (i = 0; i < size; i++) {
429 if (prod)
430 gk20a_writel(g, gp10b_slcg_perf[i].addr,
431 gp10b_slcg_perf[i].prod);
432 else
433 gk20a_writel(g, gp10b_slcg_perf[i].addr,
434 gp10b_slcg_perf[i].disable);
435 }
436}
437
438void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
439 bool prod)
440{
441 u32 i;
442 u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc);
443
444 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
445 return;
446
447 for (i = 0; i < size; i++) {
448 if (prod)
449 gk20a_writel(g, gp10b_slcg_priring[i].addr,
450 gp10b_slcg_priring[i].prod);
451 else
452 gk20a_writel(g, gp10b_slcg_priring[i].addr,
453 gp10b_slcg_priring[i].disable);
454 }
455}
456
457void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
458 bool prod)
459{
460 u32 i;
461 u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc);
462
463 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
464 return;
465
466 for (i = 0; i < size; i++) {
467 if (prod)
468 gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
469 gp10b_slcg_pwr_csb[i].prod);
470 else
471 gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
472 gp10b_slcg_pwr_csb[i].disable);
473 }
474}
475
476void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
477 bool prod)
478{
479 u32 i;
480 u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc);
481
482 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
483 return;
484
485 for (i = 0; i < size; i++) {
486 if (prod)
487 gk20a_writel(g, gp10b_slcg_pmu[i].addr,
488 gp10b_slcg_pmu[i].prod);
489 else
490 gk20a_writel(g, gp10b_slcg_pmu[i].addr,
491 gp10b_slcg_pmu[i].disable);
492 }
493}
494
495void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
496 bool prod)
497{
498 u32 i;
499 u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc);
500
501 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
502 return;
503
504 for (i = 0; i < size; i++) {
505 if (prod)
506 gk20a_writel(g, gp10b_slcg_therm[i].addr,
507 gp10b_slcg_therm[i].prod);
508 else
509 gk20a_writel(g, gp10b_slcg_therm[i].addr,
510 gp10b_slcg_therm[i].disable);
511 }
512}
513
514void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
515 bool prod)
516{
517 u32 i;
518 u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc);
519
520 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
521 return;
522
523 for (i = 0; i < size; i++) {
524 if (prod)
525 gk20a_writel(g, gp10b_slcg_xbar[i].addr,
526 gp10b_slcg_xbar[i].prod);
527 else
528 gk20a_writel(g, gp10b_slcg_xbar[i].addr,
529 gp10b_slcg_xbar[i].disable);
530 }
531}
532
533void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
534 bool prod)
535{
536 u32 i;
537 u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc);
538
539 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
540 return;
541
542 for (i = 0; i < size; i++) {
543 if (prod)
544 gk20a_writel(g, gp10b_blcg_bus[i].addr,
545 gp10b_blcg_bus[i].prod);
546 else
547 gk20a_writel(g, gp10b_blcg_bus[i].addr,
548 gp10b_blcg_bus[i].disable);
549 }
550}
551
552void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
553 bool prod)
554{
555 u32 i;
556 u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc);
557
558 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
559 return;
560
561 for (i = 0; i < size; i++) {
562 if (prod)
563 gk20a_writel(g, gp10b_blcg_ce[i].addr,
564 gp10b_blcg_ce[i].prod);
565 else
566 gk20a_writel(g, gp10b_blcg_ce[i].addr,
567 gp10b_blcg_ce[i].disable);
568 }
569}
570
571void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
572 bool prod)
573{
574 u32 i;
575 u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc);
576
577 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
578 return;
579
580 for (i = 0; i < size; i++) {
581 if (prod)
582 gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
583 gp10b_blcg_ctxsw_prog[i].prod);
584 else
585 gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
586 gp10b_blcg_ctxsw_prog[i].disable);
587 }
588}
589
590void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
591 bool prod)
592{
593 u32 i;
594 u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc);
595
596 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
597 return;
598
599 for (i = 0; i < size; i++) {
600 if (prod)
601 gk20a_writel(g, gp10b_blcg_fb[i].addr,
602 gp10b_blcg_fb[i].prod);
603 else
604 gk20a_writel(g, gp10b_blcg_fb[i].addr,
605 gp10b_blcg_fb[i].disable);
606 }
607}
608
609void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
610 bool prod)
611{
612 u32 i;
613 u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc);
614
615 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
616 return;
617
618 for (i = 0; i < size; i++) {
619 if (prod)
620 gk20a_writel(g, gp10b_blcg_fifo[i].addr,
621 gp10b_blcg_fifo[i].prod);
622 else
623 gk20a_writel(g, gp10b_blcg_fifo[i].addr,
624 gp10b_blcg_fifo[i].disable);
625 }
626}
627
628void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
629 bool prod)
630{
631 u32 i;
632 u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc);
633
634 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
635 return;
636
637 for (i = 0; i < size; i++) {
638 if (prod)
639 gk20a_writel(g, gp10b_blcg_gr[i].addr,
640 gp10b_blcg_gr[i].prod);
641 else
642 gk20a_writel(g, gp10b_blcg_gr[i].addr,
643 gp10b_blcg_gr[i].disable);
644 }
645}
646
647void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
648 bool prod)
649{
650 u32 i;
651 u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc);
652
653 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
654 return;
655
656 for (i = 0; i < size; i++) {
657 if (prod)
658 gk20a_writel(g, gp10b_blcg_ltc[i].addr,
659 gp10b_blcg_ltc[i].prod);
660 else
661 gk20a_writel(g, gp10b_blcg_ltc[i].addr,
662 gp10b_blcg_ltc[i].disable);
663 }
664}
665
666void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
667 bool prod)
668{
669 u32 i;
670 u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc);
671
672 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
673 return;
674
675 for (i = 0; i < size; i++) {
676 if (prod)
677 gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
678 gp10b_blcg_pwr_csb[i].prod);
679 else
680 gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
681 gp10b_blcg_pwr_csb[i].disable);
682 }
683}
684
685void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
686 bool prod)
687{
688 u32 i;
689 u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc);
690
691 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
692 return;
693
694 for (i = 0; i < size; i++) {
695 if (prod)
696 gk20a_writel(g, gp10b_blcg_pmu[i].addr,
697 gp10b_blcg_pmu[i].prod);
698 else
699 gk20a_writel(g, gp10b_blcg_pmu[i].addr,
700 gp10b_blcg_pmu[i].disable);
701 }
702}
703
704void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
705 bool prod)
706{
707 u32 i;
708 u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc);
709
710 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
711 return;
712
713 for (i = 0; i < size; i++) {
714 if (prod)
715 gk20a_writel(g, gp10b_blcg_xbar[i].addr,
716 gp10b_blcg_xbar[i].prod);
717 else
718 gk20a_writel(g, gp10b_blcg_xbar[i].addr,
719 gp10b_blcg_xbar[i].disable);
720 }
721}
722
723void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
724 bool prod)
725{
726 u32 i;
727 u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc);
728
729 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
730 return;
731
732 for (i = 0; i < size; i++) {
733 if (prod)
734 gk20a_writel(g, gp10b_pg_gr[i].addr,
735 gp10b_pg_gr[i].prod);
736 else
737 gk20a_writel(g, gp10b_pg_gr[i].addr,
738 gp10b_pg_gr[i].disable);
739 }
740}
741
742#endif /* __gp10b_gating_reglist_h__ */
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h
deleted file mode 100644
index 7dbc6cac..00000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include "gk20a/gk20a.h"
24
25void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
26 bool prod);
27
28void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
29 bool prod);
30
31void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
32 bool prod);
33
34void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
35 bool prod);
36
37void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
38 bool prod);
39
40void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
41 bool prod);
42
43void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
44 bool prod);
45
46void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
47 bool prod);
48
49void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
50 bool prod);
51
52void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
53 bool prod);
54
55void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
56 bool prod);
57
58void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
59 bool prod);
60
61void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
62 bool prod);
63
64void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
65 bool prod);
66
67void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
68 bool prod);
69
70void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
71 bool prod);
72
73void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
74 bool prod);
75
76void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
77 bool prod);
78
79void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
80 bool prod);
81
82void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
83 bool prod);
84
85void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
86 bool prod);
87
88void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
89 bool prod);
90
91void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
92 bool prod);
93
94void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
95 bool prod);
96
97void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
98 bool prod);
99
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index e4bf0fd7..6d7d32ac 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -48,7 +48,7 @@
48#include "gp10b/pmu_gp10b.h" 48#include "gp10b/pmu_gp10b.h"
49#include "gp10b/gr_ctx_gp10b.h" 49#include "gp10b/gr_ctx_gp10b.h"
50#include "gp10b/fifo_gp10b.h" 50#include "gp10b/fifo_gp10b.h"
51#include "gp10b/gp10b_gating_reglist.h" 51#include "clock_gating/gp10b_gating_reglist.h"
52#include "gp10b/regops_gp10b.h" 52#include "gp10b/regops_gp10b.h"
53#include "gp10b/therm_gp10b.h" 53#include "gp10b/therm_gp10b.h"
54#include "gp10b/priv_ring_gp10b.h" 54#include "gp10b/priv_ring_gp10b.h"
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 23:14:44 -0400