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author | Seema Khowala <seemaj@nvidia.com> | 2017-06-22 16:43:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-06 15:04:43 -0400 |
commit | d8c0144f8b45ef8a94fc696efaa0c782c4c787af (patch) | |
tree | 07c7463570e0451731dcd29091e1a254b96cd409 /drivers/gpu/nvgpu/gp10b | |
parent | 0852c9f1aba1654e380ccdd13cd0540fbb5a8ab0 (diff) |
gpu: nvgpu: add clear_sm_hww gr ops
Required for multiple SM support and t19x SM
register address changes
JIRA GPUT19X-75
Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 27d609d1..4ff306e0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1835,7 +1835,8 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
1835 | /* reset the HWW errors after locking down */ | 1835 | /* reset the HWW errors after locking down */ |
1836 | global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, | 1836 | global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, |
1837 | gpc, tpc, sm); | 1837 | gpc, tpc, sm); |
1838 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); | 1838 | g->ops.gr.clear_sm_hww(g, |
1839 | gpc, tpc, sm, global_esr_copy); | ||
1839 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1840 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1840 | "CILP: HWWs cleared for gpc %d tpc %d\n", | 1841 | "CILP: HWWs cleared for gpc %d tpc %d\n", |
1841 | gpc, tpc); | 1842 | gpc, tpc); |