nvgpu: gv11b: Rearrange gr function

Moved gv11b_detect_ecc_enabled_units function
from gv11b.c to gr_gv11b.c, as this is being
used only in gr_gv11b file.

In order to avoid GR code touching fuse registers,
as it need to include fuse HW headers in GR code,
introduced two fuse HALs which are being called
from GR code. is_opt_ecc_enable for checking
whether ecc enable bit is set in fuse register
and is_opt_feature_overide_disable for checking
whether feature override disable bit is set in
fuse register.

Initialized fuse HAL functions for chips that
make use of those HAL functions.

JIRA NVGPU-615

Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775564
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 37 insertions, 21 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c
index c1fc6be7..52087676 100644
--- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP10B FUSE
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -91,3 +91,14 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
 
         return 0;
 }
+
+bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g)
+{
+        return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U;
+}
+
+bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g)
+{
+        return gk20a_readl(g,
+                        fuse_opt_feature_fuses_override_disable_r()) != 0U;
+}
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h
index 1acb45d1..d9037e22 100644
--- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * GP10B FUSE
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,5 +28,7 @@
 struct gk20a;
 
 int gp10b_fuse_check_priv_security(struct gk20a *g);
+bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g);
+bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g);
 
 #endif
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c
index 51dc4301..7991944c 100644
--- a/drivers/gpu/nvgpu/gp10b/gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gp10b.c
@@ -1,7 +1,7 @@
 /*
  * GP10B Graphics
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,15 +28,13 @@
 
 #include "gp10b.h"
 
-#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 
 static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 {
-        u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
-        u32 opt_feature_fuses_override_disable =
-                        gk20a_readl(g,
-                                fuse_opt_feature_fuses_override_disable_r());
+        bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g);
+        bool opt_feature_fuses_override_disable =
+                        g->ops.fuse.is_opt_feature_override_disable(g);
         u32 fecs_feature_override_ecc =
                                 gk20a_readl(g,
                                         gr_fecs_feature_override_ecc_r());
@@ -51,9 +49,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
         } else {
                 /* SM LRF */
                 if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
-                                                fecs_feature_override_ecc)) {
+                                        fecs_feature_override_ecc) == 1U) {
                         if (gr_fecs_feature_override_ecc_sm_lrf_v(
-                                                fecs_feature_override_ecc)) {
+                                        fecs_feature_override_ecc) == 1U) {
                                 __nvgpu_set_enabled(g,
                                                 NVGPU_ECC_ENABLED_SM_LRF, true);
                         }
@@ -66,9 +64,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 
                 /* SM SHM */
                 if (gr_fecs_feature_override_ecc_sm_shm_override_v(
-                                                fecs_feature_override_ecc)) {
+                                        fecs_feature_override_ecc) == 1U) {
                         if (gr_fecs_feature_override_ecc_sm_shm_v(
-                                                fecs_feature_override_ecc)) {
+                                        fecs_feature_override_ecc) == 1U) {
                                 __nvgpu_set_enabled(g,
                                                 NVGPU_ECC_ENABLED_SM_SHM, true);
                         }
@@ -81,9 +79,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 
                 /* TEX */
                 if (gr_fecs_feature_override_ecc_tex_override_v(
-                                                fecs_feature_override_ecc)) {
+                                        fecs_feature_override_ecc) == 1U) {
                         if (gr_fecs_feature_override_ecc_tex_v(
-                                                fecs_feature_override_ecc)) {
+                                        fecs_feature_override_ecc) == 1U) {
                                 __nvgpu_set_enabled(g,
                                                 NVGPU_ECC_ENABLED_TEX, true);
                         }
@@ -96,9 +94,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 
                 /* LTC */
                 if (gr_fecs_feature_override_ecc_ltc_override_v(
-                                                fecs_feature_override_ecc)) {
+                                        fecs_feature_override_ecc) == 1U) {
                         if (gr_fecs_feature_override_ecc_ltc_v(
-                                                fecs_feature_override_ecc)) {
+                                        fecs_feature_override_ecc) == 1U) {
                                 __nvgpu_set_enabled(g,
                                                 NVGPU_ECC_ENABLED_LTC, true);
                         }
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 424c8490..16eddeca 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -43,7 +43,6 @@
 #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
-#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
 
 #define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000
 
@@ -2022,11 +2021,14 @@ u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
 
 u32 get_ecc_override_val(struct gk20a *g)
 {
-        u32 val;
+        bool en = false;
 
-        val = gk20a_readl(g, fuse_opt_ecc_en_r());
-        if (val)
-                return gk20a_readl(g, gr_fecs_feature_override_ecc_r());
+        if (g->ops.fuse.is_opt_ecc_enable) {
+                en = g->ops.fuse.is_opt_ecc_enable(g);
+                if (en) {
+                        return gk20a_readl(g, gr_fecs_feature_override_ecc_r());
+                }
+        }
 
         return 0;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index bbfce287..94adf727 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -694,6 +694,9 @@ static const struct gpu_ops gp10b_ops = {
         },
         .fuse = {
                 .check_priv_security = gp10b_fuse_check_priv_security,
+                .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
+                .is_opt_feature_override_disable =
+                        gp10b_fuse_is_opt_feature_override_disable,
         },
         .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
         .get_litter_value = gp10b_get_litter_value,