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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-05-24 18:25:41 -0400
committerTejal Kudav <tkudav@nvidia.com>2018-06-14 09:44:07 -0400
commitd71d38087ded679f60714dae3a859523a19df04f (patch)
tree61439d294705ef91ce08ae4c02d4921eec943283 /drivers/gpu/nvgpu/gp10b
parent5215d65c25b5e76c19d9d12b03c52f69e2d40227 (diff)
gpu: nvgpu: Separate timer from bus
Code touching timer registers was combined with bus code. They're two logically separate register spaces, so separate the code accordingly. JIRA NVGPU-588 Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730893 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index defec775..0106f6c9 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -24,6 +24,7 @@
24 24
25#include "common/bus/bus_gk20a.h" 25#include "common/bus/bus_gk20a.h"
26#include "common/clock_gating/gp10b_gating_reglist.h" 26#include "common/clock_gating/gp10b_gating_reglist.h"
27#include "common/ptimer/ptimer_gk20a.h"
27 28
28#include "gk20a/gk20a.h" 29#include "gk20a/gk20a.h"
29#include "gk20a/fifo_gk20a.h" 30#include "gk20a/fifo_gk20a.h"
@@ -69,7 +70,7 @@
69#include <nvgpu/debug.h> 70#include <nvgpu/debug.h>
70#include <nvgpu/bug.h> 71#include <nvgpu/bug.h>
71#include <nvgpu/enabled.h> 72#include <nvgpu/enabled.h>
72#include <nvgpu/bus.h> 73#include <nvgpu/ptimer.h>
73#include <nvgpu/ctxsw_trace.h> 74#include <nvgpu/ctxsw_trace.h>
74#include <nvgpu/error_notifier.h> 75#include <nvgpu/error_notifier.h>
75 76
@@ -650,11 +651,14 @@ static const struct gpu_ops gp10b_ops = {
650 .bus = { 651 .bus = {
651 .init_hw = gk20a_bus_init_hw, 652 .init_hw = gk20a_bus_init_hw,
652 .isr = gk20a_bus_isr, 653 .isr = gk20a_bus_isr,
653 .read_ptimer = gk20a_read_ptimer,
654 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
655 .bar1_bind = gk20a_bus_bar1_bind, 654 .bar1_bind = gk20a_bus_bar1_bind,
656 .set_bar0_window = gk20a_bus_set_bar0_window, 655 .set_bar0_window = gk20a_bus_set_bar0_window,
657 }, 656 },
657 .ptimer = {
658 .isr = gk20a_ptimer_isr,
659 .read_ptimer = gk20a_read_ptimer,
660 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
661 },
658#if defined(CONFIG_GK20A_CYCLE_STATS) 662#if defined(CONFIG_GK20A_CYCLE_STATS)
659 .css = { 663 .css = {
660 .enable_snapshot = css_hw_enable_snapshot, 664 .enable_snapshot = css_hw_enable_snapshot,
@@ -705,6 +709,7 @@ int gp10b_init_hal(struct gk20a *g)
705 gops->debugger = gp10b_ops.debugger; 709 gops->debugger = gp10b_ops.debugger;
706 gops->dbg_session_ops = gp10b_ops.dbg_session_ops; 710 gops->dbg_session_ops = gp10b_ops.dbg_session_ops;
707 gops->bus = gp10b_ops.bus; 711 gops->bus = gp10b_ops.bus;
712 gops->ptimer = gp10b_ops.ptimer;
708#if defined(CONFIG_GK20A_CYCLE_STATS) 713#if defined(CONFIG_GK20A_CYCLE_STATS)
709 gops->css = gp10b_ops.css; 714 gops->css = gp10b_ops.css;
710#endif 715#endif