gpu: nvgpu: Remove privsecurity flag from gpu_ops

Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.

The new common flag is NVGPU_SEC_PRIVSECURITY

Jira NVGPU-74

Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525713
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

5 files changed, 22 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 67a38e6e..d2b86e51 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -2368,9 +2368,11 @@ int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch)
         return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false);
 }
 
-void gp10b_init_gr(struct gpu_ops *gops)
+void gp10b_init_gr(struct gk20a *g)
 {
-        gm20b_init_gr(gops);
+        struct gpu_ops *gops = &g->ops;
+
+        gm20b_init_gr(g);
         gops->gr.init_fs_state = gr_gp10b_init_fs_state;
         gops->gr.init_preemption_state = gr_gp10b_init_preemption_state;
         gops->gr.is_valid_class = gr_gp10b_is_valid_class;
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index aac9eb65..161fec87 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -20,7 +20,7 @@
 
 #include "gk20a/mm_gk20a.h"
 
-struct gpu_ops;
+struct gk20a;
 struct gr_gk20a_isr_data;
 
 enum {
@@ -41,7 +41,7 @@ enum {
 #define NVC0C0_SET_SHADER_EXCEPTIONS            0x1528
 #define NVC0C0_SET_RD_COALESCE                  0x0228
 
-void gp10b_init_gr(struct gpu_ops *ops);
+void gp10b_init_gr(struct gk20a *g);
 int gr_gp10b_init_fs_state(struct gk20a *g);
 int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
                         struct nvgpu_mem *mem);
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 818949f0..6b4fbf40 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -368,49 +368,49 @@ int gp10b_init_hal(struct gk20a *g)
 
 #ifdef CONFIG_TEGRA_ACR
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                gops->privsecurity = 0;
+                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
                 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
         } else if (g->is_virtual) {
-                gops->privsecurity = 1;
+                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
                 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
         } else {
                 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
                 if (val) {
-                        gops->privsecurity = 1;
+                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
                         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
                 } else {
                         gk20a_dbg_info("priv security is disabled in HW");
-                        gops->privsecurity = 0;
+                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
                         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
                 }
         }
 #else
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 gk20a_dbg_info("running simulator with PRIV security disabled");
-                gops->privsecurity = 0;
+                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
                 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
         } else {
                 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
                 if (val) {
                         gk20a_dbg_info("priv security is not supported but enabled");
-                        gops->privsecurity = 1;
+                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
                         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
                         return -EPERM;
                 } else {
-                        gops->privsecurity = 0;
+                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
                         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
                 }
         }
 #endif
 
         g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
-        gp10b_init_gr(gops);
+        gp10b_init_gr(g);
         gp10b_init_fecs_trace_ops(gops);
         gp10b_init_fb(gops);
         gp10b_init_ce(gops);
         gp10b_init_gr_ctx(gops);
         gp10b_init_mm(gops);
-        gp10b_init_pmu_ops(gops);
+        gp10b_init_pmu_ops(g);
         gp10b_init_regops(gops);
         gp10b_init_therm_ops(gops);
         gk20a_init_pramin_ops(gops);
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
index dbaf3ebf..e9a9b922 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -16,6 +16,7 @@
 #include <nvgpu/pmu.h>
 #include <nvgpu/log.h>
 #include <nvgpu/fuse.h>
+#include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/pmu_gk20a.h"
@@ -391,10 +392,11 @@ static bool gp10b_is_pmu_supported(struct gk20a *g)
         return true;
 }
 
-void gp10b_init_pmu_ops(struct gpu_ops *gops)
+void gp10b_init_pmu_ops(struct gk20a *g)
 {
+        struct gpu_ops *gops = &g->ops;
         gops->pmu.is_pmu_supported = gp10b_is_pmu_supported;
-        if (gops->privsecurity) {
+        if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
                 gm20b_init_secure_pmu(gops);
                 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
                 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
index 9fc6228d..5ba7bb9b 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
@@ -16,7 +16,9 @@
 #ifndef __PMU_GP10B_H_
 #define __PMU_GP10B_H_
 
-void gp10b_init_pmu_ops(struct gpu_ops *gops);
+struct gk20a;
+
+void gp10b_init_pmu_ops(struct gk20a *g);
 int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
 int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
 void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr);