diff options
author | Vaibhav Kachore <vkachore@nvidia.com> | 2018-02-22 06:15:30 -0500 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:08 -0400 |
commit | ca3215c6b23c7d855ced899d8090aaa8ce9a9fa3 (patch) | |
tree | 710114451d4838f82a9e9998db52b81cf76d68c9 /drivers/gpu/nvgpu/gp10b | |
parent | 97d697a8481ca0c348102f04165903e3205302ed (diff) |
gpu: nvgpu: add support for FECS VA
- On t186, ucode expects physical address to be
programmed for FECS trace buffer.
- On t194, ucode expects GPU VA to be programmed
for FECS trace buffer. This patch adds extra
support to handle this change for linux native.
- Increase the size of FECS trace buffer (as few
entries were getting dropped due to overflow of
FECS trace buffer.)
- This moves FECS trace buffer handling in global
context buffer.
- This adds extra check for updation of mailbox1
register. (Bug 200417403)
EVLR-2077
Change-Id: I7c3324ce9341976a1375e0afe6c53c424a053723
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1536028
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 62164d16..80e07b78 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -732,6 +732,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
732 | 732 | ||
733 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 733 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
734 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 734 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
735 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); | ||
735 | 736 | ||
736 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 737 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
737 | if (gops->fuse.check_priv_security(g)) | 738 | if (gops->fuse.check_priv_security(g)) |