diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-01-12 00:15:51 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-16 07:53:38 -0500 |
commit | c8d82d465c03b4d7e18ab1ba1bfce6581d2aad6e (patch) | |
tree | 4e4fee5ea1d2bb214a886ca11ab3fd27c339d942 /drivers/gpu/nvgpu/gp10b | |
parent | a177c8e2383f3e7a5b3c8cd5d204e4594bb04875 (diff) |
gpu: nvgpu: HAL to query LPWR feature support
HAL to query LPWR feautre's RPPG/MSCG support
based on current pstate configured.
JIRA DNVGPU-71
Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1283916
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index fc535985..cf216941 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -487,6 +487,7 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) | |||
487 | gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init; | 487 | gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init; |
488 | gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list; | 488 | gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list; |
489 | gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list; | 489 | gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list; |
490 | gops->pmu.pmu_is_lpwr_feature_supported = NULL; | ||
490 | gops->pmu.pmu_lpwr_enable_pg = NULL; | 491 | gops->pmu.pmu_lpwr_enable_pg = NULL; |
491 | gops->pmu.pmu_lpwr_disable_pg = NULL; | 492 | gops->pmu.pmu_lpwr_disable_pg = NULL; |
492 | gops->pmu.pmu_pg_param_post_init = NULL; | 493 | gops->pmu.pmu_pg_param_post_init = NULL; |