diff options
author | Sunny He <suhe@nvidia.com> | 2017-07-28 21:36:52 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-02 17:43:25 -0400 |
commit | a15e110a9b790f55a5c6e257cfbf7f7235f5a334 (patch) | |
tree | 199209146e3e67927c13e2ece240de40f973e1ea /drivers/gpu/nvgpu/gp10b | |
parent | 43ae97000be786e4118d431637f05b1462e296c4 (diff) |
gpu: nvgpu: Reorg regops HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
regops sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I7e2ccf158a8e7efa453a3326e86146660f18926f
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530135
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 25 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 65 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/regops_gp10b.h | 18 |
3 files changed, 54 insertions, 54 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a2aacd2e..e2479530 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -313,6 +313,29 @@ static const struct gpu_ops gp10b_ops = { | |||
313 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, | 313 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, |
314 | .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, | 314 | .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, |
315 | }, | 315 | }, |
316 | .regops = { | ||
317 | .get_global_whitelist_ranges = | ||
318 | gp10b_get_global_whitelist_ranges, | ||
319 | .get_global_whitelist_ranges_count = | ||
320 | gp10b_get_global_whitelist_ranges_count, | ||
321 | .get_context_whitelist_ranges = | ||
322 | gp10b_get_context_whitelist_ranges, | ||
323 | .get_context_whitelist_ranges_count = | ||
324 | gp10b_get_context_whitelist_ranges_count, | ||
325 | .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, | ||
326 | .get_runcontrol_whitelist_count = | ||
327 | gp10b_get_runcontrol_whitelist_count, | ||
328 | .get_runcontrol_whitelist_ranges = | ||
329 | gp10b_get_runcontrol_whitelist_ranges, | ||
330 | .get_runcontrol_whitelist_ranges_count = | ||
331 | gp10b_get_runcontrol_whitelist_ranges_count, | ||
332 | .get_qctl_whitelist = gp10b_get_qctl_whitelist, | ||
333 | .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, | ||
334 | .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges, | ||
335 | .get_qctl_whitelist_ranges_count = | ||
336 | gp10b_get_qctl_whitelist_ranges_count, | ||
337 | .apply_smpc_war = gp10b_apply_smpc_war, | ||
338 | }, | ||
316 | .mc = { | 339 | .mc = { |
317 | .intr_enable = mc_gp10b_intr_enable, | 340 | .intr_enable = mc_gp10b_intr_enable, |
318 | .intr_unit_config = mc_gp10b_intr_unit_config, | 341 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -390,6 +413,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
390 | gops->fecs_trace = gp10b_ops.fecs_trace; | 413 | gops->fecs_trace = gp10b_ops.fecs_trace; |
391 | gops->pramin = gp10b_ops.pramin; | 414 | gops->pramin = gp10b_ops.pramin; |
392 | gops->therm = gp10b_ops.therm; | 415 | gops->therm = gp10b_ops.therm; |
416 | gops->regops = gp10b_ops.regops; | ||
393 | gops->mc = gp10b_ops.mc; | 417 | gops->mc = gp10b_ops.mc; |
394 | gops->debug = gp10b_ops.debug; | 418 | gops->debug = gp10b_ops.debug; |
395 | gops->dbg_session_ops = gp10b_ops.dbg_session_ops; | 419 | gops->dbg_session_ops = gp10b_ops.dbg_session_ops; |
@@ -452,7 +476,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
452 | gp10b_init_fb(gops); | 476 | gp10b_init_fb(gops); |
453 | gp10b_init_mm(gops); | 477 | gp10b_init_mm(gops); |
454 | gp10b_init_pmu_ops(g); | 478 | gp10b_init_pmu_ops(g); |
455 | gp10b_init_regops(gops); | ||
456 | 479 | ||
457 | g->name = "gp10b"; | 480 | g->name = "gp10b"; |
458 | 481 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c index 885221df..f90ecaa6 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger Driver Register Ops | 2 | * Tegra GK20A GPU Debugger Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -406,105 +406,68 @@ static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = { | |||
406 | static const u32 gp10b_qctl_whitelist_ranges_count = | 406 | static const u32 gp10b_qctl_whitelist_ranges_count = |
407 | ARRAY_SIZE(gp10b_qctl_whitelist_ranges); | 407 | ARRAY_SIZE(gp10b_qctl_whitelist_ranges); |
408 | 408 | ||
409 | static const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) | 409 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) |
410 | { | 410 | { |
411 | return gp10b_global_whitelist_ranges; | 411 | return gp10b_global_whitelist_ranges; |
412 | } | 412 | } |
413 | 413 | ||
414 | static int gp10b_get_global_whitelist_ranges_count(void) | 414 | int gp10b_get_global_whitelist_ranges_count(void) |
415 | { | 415 | { |
416 | return gp10b_global_whitelist_ranges_count; | 416 | return gp10b_global_whitelist_ranges_count; |
417 | } | 417 | } |
418 | 418 | ||
419 | static const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void) | 419 | const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void) |
420 | { | 420 | { |
421 | return gp10b_global_whitelist_ranges; | 421 | return gp10b_global_whitelist_ranges; |
422 | } | 422 | } |
423 | 423 | ||
424 | static int gp10b_get_context_whitelist_ranges_count(void) | 424 | int gp10b_get_context_whitelist_ranges_count(void) |
425 | { | 425 | { |
426 | return gp10b_global_whitelist_ranges_count; | 426 | return gp10b_global_whitelist_ranges_count; |
427 | } | 427 | } |
428 | 428 | ||
429 | static const u32 *gp10b_get_runcontrol_whitelist(void) | 429 | const u32 *gp10b_get_runcontrol_whitelist(void) |
430 | { | 430 | { |
431 | return gp10b_runcontrol_whitelist; | 431 | return gp10b_runcontrol_whitelist; |
432 | } | 432 | } |
433 | 433 | ||
434 | static int gp10b_get_runcontrol_whitelist_count(void) | 434 | int gp10b_get_runcontrol_whitelist_count(void) |
435 | { | 435 | { |
436 | return gp10b_runcontrol_whitelist_count; | 436 | return gp10b_runcontrol_whitelist_count; |
437 | } | 437 | } |
438 | 438 | ||
439 | static const | 439 | const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void) |
440 | struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void) | ||
441 | { | 440 | { |
442 | return gp10b_runcontrol_whitelist_ranges; | 441 | return gp10b_runcontrol_whitelist_ranges; |
443 | } | 442 | } |
444 | 443 | ||
445 | static int gp10b_get_runcontrol_whitelist_ranges_count(void) | 444 | int gp10b_get_runcontrol_whitelist_ranges_count(void) |
446 | { | 445 | { |
447 | return gp10b_runcontrol_whitelist_ranges_count; | 446 | return gp10b_runcontrol_whitelist_ranges_count; |
448 | } | 447 | } |
449 | 448 | ||
450 | static const u32 *gp10b_get_qctl_whitelist(void) | 449 | const u32 *gp10b_get_qctl_whitelist(void) |
451 | { | 450 | { |
452 | return gp10b_qctl_whitelist; | 451 | return gp10b_qctl_whitelist; |
453 | } | 452 | } |
454 | 453 | ||
455 | static int gp10b_get_qctl_whitelist_count(void) | 454 | int gp10b_get_qctl_whitelist_count(void) |
456 | { | 455 | { |
457 | return gp10b_qctl_whitelist_count; | 456 | return gp10b_qctl_whitelist_count; |
458 | } | 457 | } |
459 | 458 | ||
460 | static const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void) | 459 | const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void) |
461 | { | 460 | { |
462 | return gp10b_qctl_whitelist_ranges; | 461 | return gp10b_qctl_whitelist_ranges; |
463 | } | 462 | } |
464 | 463 | ||
465 | static int gp10b_get_qctl_whitelist_ranges_count(void) | 464 | int gp10b_get_qctl_whitelist_ranges_count(void) |
466 | { | 465 | { |
467 | return gp10b_qctl_whitelist_ranges_count; | 466 | return gp10b_qctl_whitelist_ranges_count; |
468 | } | 467 | } |
469 | 468 | ||
470 | static int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | 469 | int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) |
471 | { | 470 | { |
472 | /* Not needed on gp10b */ | 471 | /* Not needed on gp10b */ |
473 | return 0; | 472 | return 0; |
474 | } | 473 | } |
475 | |||
476 | void gp10b_init_regops(struct gpu_ops *gops) | ||
477 | { | ||
478 | gops->regops.get_global_whitelist_ranges = | ||
479 | gp10b_get_global_whitelist_ranges; | ||
480 | gops->regops.get_global_whitelist_ranges_count = | ||
481 | gp10b_get_global_whitelist_ranges_count; | ||
482 | |||
483 | gops->regops.get_context_whitelist_ranges = | ||
484 | gp10b_get_context_whitelist_ranges; | ||
485 | gops->regops.get_context_whitelist_ranges_count = | ||
486 | gp10b_get_context_whitelist_ranges_count; | ||
487 | |||
488 | gops->regops.get_runcontrol_whitelist = | ||
489 | gp10b_get_runcontrol_whitelist; | ||
490 | gops->regops.get_runcontrol_whitelist_count = | ||
491 | gp10b_get_runcontrol_whitelist_count; | ||
492 | |||
493 | gops->regops.get_runcontrol_whitelist_ranges = | ||
494 | gp10b_get_runcontrol_whitelist_ranges; | ||
495 | gops->regops.get_runcontrol_whitelist_ranges_count = | ||
496 | gp10b_get_runcontrol_whitelist_ranges_count; | ||
497 | |||
498 | gops->regops.get_qctl_whitelist = | ||
499 | gp10b_get_qctl_whitelist; | ||
500 | gops->regops.get_qctl_whitelist_count = | ||
501 | gp10b_get_qctl_whitelist_count; | ||
502 | |||
503 | gops->regops.get_qctl_whitelist_ranges = | ||
504 | gp10b_get_qctl_whitelist_ranges; | ||
505 | gops->regops.get_qctl_whitelist_ranges_count = | ||
506 | gp10b_get_qctl_whitelist_ranges_count; | ||
507 | |||
508 | gops->regops.apply_smpc_war = | ||
509 | gp10b_apply_smpc_war; | ||
510 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h index 8727951a..524a42c8 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Tegra GP10B GPU Debugger Driver Register Ops | 3 | * Tegra GP10B GPU Debugger Driver Register Ops |
4 | * | 4 | * |
5 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | 7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms and conditions of the GNU General Public License, | 8 | * under the terms and conditions of the GNU General Public License, |
@@ -19,6 +19,20 @@ | |||
19 | #ifndef __REGOPS_GP10B_H_ | 19 | #ifndef __REGOPS_GP10B_H_ |
20 | #define __REGOPS_GP10B_H_ | 20 | #define __REGOPS_GP10B_H_ |
21 | 21 | ||
22 | void gp10b_init_regops(struct gpu_ops *gops); | 22 | struct dbg_session_gk20a; |
23 | |||
24 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void); | ||
25 | int gp10b_get_global_whitelist_ranges_count(void); | ||
26 | const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void); | ||
27 | int gp10b_get_context_whitelist_ranges_count(void); | ||
28 | const u32 *gp10b_get_runcontrol_whitelist(void); | ||
29 | int gp10b_get_runcontrol_whitelist_count(void); | ||
30 | const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void); | ||
31 | int gp10b_get_runcontrol_whitelist_ranges_count(void); | ||
32 | const u32 *gp10b_get_qctl_whitelist(void); | ||
33 | int gp10b_get_qctl_whitelist_count(void); | ||
34 | const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void); | ||
35 | int gp10b_get_qctl_whitelist_ranges_count(void); | ||
36 | int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | ||
23 | 37 | ||
24 | #endif /* __REGOPS_GP10B_H_ */ | 38 | #endif /* __REGOPS_GP10B_H_ */ |