nvgpu: gp10b: MISRA Rule 21.2 header guard fixes

MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gp10b by renaming
them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when
there is no keyword repetition between file name and directory or
'NVGPU_HEADER-NAME' when there is repetition.

JIRA NVGPU-1028

Change-Id: If66863e568d74a0bc7473cf8decacece1e1069f3
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1819163
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

8 files changed, 27 insertions, 27 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
index 525599af..4fa27d1e 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
@@ -21,8 +21,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __CE_GP10B_H__
-#define __CE_GP10B_H__
+#ifndef NVGPU_CE_GP10B_H
+#define NVGPU_CE_GP10B_H
 
 #include <nvgpu/types.h>
 
@@ -31,4 +31,4 @@ struct gk20a;
 void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 
-#endif /*__CE2_GP10B_H__*/
+#endif /* NVGPU_CE_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
index e5101db0..73145f9e 100644
--- a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
@@ -20,9 +20,9 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef __ECC_GP10B_H__
-#define __ECC_GP10B_H__
+#ifndef NVGPU_ECC_GP10B_H
+#define NVGPU_ECC_GP10B_H
 
 int gp10b_ecc_init(struct gk20a *g);
 
-#endif
+#endif /* NVGPU_ECC_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
index f192617c..0eda975b 100644
--- a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * GP10B GPU FECS traces
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,11 +22,11 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_FECS_TRACE_GP10B_H_
-#define _NVGPU_FECS_TRACE_GP10B_H_
+#ifndef NVGPU_FECS_TRACE_GP10B_H
+#define NVGPU_FECS_TRACE_GP10B_H
 
 struct gk20a;
 
 int gp10b_fecs_trace_flush(struct gk20a *g);
 
-#endif
+#endif /* NVGPU_FECS_TRACE_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
index b409b442..25cc027f 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * GP10B Graphics Context
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,8 +21,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __GR_CTX_GM10B_H__
-#define __GR_CTX_GM10B_H__
+#ifndef NVGPU_GR_CTX_GP10B_H
+#define NVGPU_GR_CTX_GP10B_H
 
 #include "gk20a/gr_ctx_gk20a.h"
 
@@ -32,4 +32,4 @@
 int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name);
 bool gr_gp10b_is_firmware_defined(void);
 
-#endif /*__GR_CTX_GP10B_H__*/
+#endif /* NVGPU_GR_CTX_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 31e1e6e9..2ae44e04 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GR_GP10B_H_
-#define _NVGPU_GR_GP10B_H_
+#ifndef NVGPU_GR_GP10B_H
+#define NVGPU_GR_GP10B_H
 
 #include "gk20a/mm_gk20a.h"
 
@@ -156,4 +156,4 @@ unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
 bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
                                 bool *cilp_preempt_pending);
 
-#endif
+#endif /* NVGPU_GR_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
index cf3c295d..6ba80b88 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * GP10B Tegra HAL interface
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,10 +22,10 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_HAL_GP10B_H
-#define _NVGPU_HAL_GP10B_H
+#ifndef NVGPU_HAL_GP10B_H
+#define NVGPU_HAL_GP10B_H
 struct gk20a;
 
 int gp10b_init_hal(struct gk20a *gops);
 int gp10b_get_litter_value(struct gk20a *g, int value);
-#endif
+#endif /* NVGPU_HAL_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
index 4fd4c7c4..9fe2ab7f 100644
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef __PMU_GP10B_H_
-#define __PMU_GP10B_H_
+#ifndef NVGPU_PMU_GP10B_H
+#define NVGPU_PMU_GP10B_H
 
 struct gk20a;
 
@@ -38,4 +38,4 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
 int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
 void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr);
 
-#endif /*__PMU_GP10B_H_*/
+#endif /* NVGPU_PMU_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
index e8b9f325..9971b0d2 100644
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
@@ -22,8 +22,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __REGOPS_GP10B_H_
-#define __REGOPS_GP10B_H_
+#ifndef NVGPU_REGOPS_GP10B_H
+#define NVGPU_REGOPS_GP10B_H
 
 struct dbg_session_gk20a;
 
@@ -41,4 +41,4 @@ const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void);
 u64 gp10b_get_qctl_whitelist_ranges_count(void);
 int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
-#endif /* __REGOPS_GP10B_H_ */
+#endif /* NVGPU_REGOPS_GP10B_H */