gpu: nvgpu: Reorg ce2 HAL initialization

Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the ce2
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I7dfd5e8dcd4d6f3623d1b795b6b2e15ff356a13a
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509632
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

3 files changed, 8 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
index 1fff37fb..59a6ee21 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
@@ -54,7 +54,7 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
         return;
 }
 
-static int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
+int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 {
         int ops = 0;
         u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
@@ -70,8 +70,3 @@ static int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 
         return ops;
 }
-void gp10b_init_ce(struct gpu_ops *gops)
-{
-        gops->ce2.isr_stall = gp10b_ce_isr;
-        gops->ce2.isr_nonstall = gp10b_ce_nonstall_isr;
-}
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
index 134c2ddb..f88e0ae1 100644
--- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * Pascal GPU series Copy Engine.
  *
- * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -21,7 +21,7 @@
 #include "gk20a/channel_gk20a.h"
 #include "gk20a/tsg_gk20a.h"
 
-void gp10b_init_ce(struct gpu_ops *gops);
 void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
+int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 
 #endif /*__CE2_GP10B_H__*/
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 6b4fbf40..feac284b 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -165,6 +165,10 @@ static const struct gpu_ops gp10b_ops = {
                 .sync_debugfs = gp10b_ltc_sync_debugfs,
 #endif
         },
+        .ce2 = {
+                .isr_stall = gp10b_ce_isr,
+                .isr_nonstall = gp10b_ce_nonstall_isr,
+        },
         .clock_gating = {
                 .slcg_bus_load_gating_prod =
                         gp10b_slcg_bus_load_gating_prod,
@@ -345,6 +349,7 @@ int gp10b_init_hal(struct gk20a *g)
         u32 val;
 
         gops->ltc = gp10b_ops.ltc;
+        gops->ce2 = gp10b_ops.ce2;
         gops->clock_gating = gp10b_ops.clock_gating;
         gops->fifo = gp10b_ops.fifo;
         gops->mc = gp10b_ops.mc;
@@ -407,7 +412,6 @@ int gp10b_init_hal(struct gk20a *g)
         gp10b_init_gr(g);
         gp10b_init_fecs_trace_ops(gops);
         gp10b_init_fb(gops);
-        gp10b_init_ce(gops);
         gp10b_init_gr_ctx(gops);
         gp10b_init_mm(gops);
         gp10b_init_pmu_ops(g);