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author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-12-03 02:35:37 -0500 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:52:03 -0500 |
commit | 945e5e6832bd2461b9eafa61e8dd06b793a6f6b9 (patch) | |
tree | 4871910ba170c3fa81b869628ca27d76509a1938 /drivers/gpu/nvgpu/gp10b | |
parent | 5d54f4660cfd5f2abee41ac63bc5fe1a1c43a87d (diff) |
gpu: nvgpu: gp10b: Correct SMMU bit number
Bit 36 is the correct bit to indicate SMMU translation.
Bug 1580756
Change-Id: I761e70265d5981b07940f1d43716416829993827
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/658827
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index a0b6a7d1..ff248f51 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -18,7 +18,7 @@ | |||
18 | 18 | ||
19 | u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) | 19 | u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) |
20 | { | 20 | { |
21 | return 37; | 21 | return 36; |
22 | } | 22 | } |
23 | 23 | ||
24 | void gp10b_init_mm(struct gpu_ops *gops) | 24 | void gp10b_init_mm(struct gpu_ops *gops) |