gpu: nvgpu: fix priv error register reads

Current code does not compute priv error register offsets
properly. This leads to invalid decoding of priv errors, and
can also trigger additional priv errors.

- add GPU_LIT_GPC_PRIV_STRIDE define
- return proj_gpc_priv_stride for GPU_LIT_GPC_PRIV_STRIDE in hals
- use GPU_LIT_GPC_PRIV_STRIDE instead of GPU_LIT_GPC_STRIDE in
  g->ops.priv_ring.isr() to compute priv error register offsets.

Bug 2093058

Change-Id: Ia7c36ccba0441126784bb0e00452f2cf1196ef71
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1682118
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 4 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 825d11e5..dd413c5a 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -181,7 +181,9 @@ int gp10b_get_litter_value(struct gk20a *g, int value)
         case GPU_LIT_DMA_COPY_CLASS:
                 ret = PASCAL_DMA_COPY_A;
                 break;
-
+        case GPU_LIT_GPC_PRIV_STRIDE:
+                ret = proj_gpc_priv_stride_v();
+                break;
         default:
                 nvgpu_err(g, "Missing definition %d", value);
                 BUG();
diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
index e7777871..0fac76f2 100644
--- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c
@@ -145,7 +145,7 @@ void gp10b_priv_ring_isr(struct gk20a *g)
         }
 
         if (status1) {
-                gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+                gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
                 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
                         offset = gpc * gpc_stride;
                         if (status1 & BIT(gpc)) {