diff options
author | Richard Zhao <rizhao@nvidia.com> | 2017-06-27 14:20:58 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-30 01:34:35 -0400 |
commit | 7d584bf868e53638f5c05b588dcd307e71cf9c82 (patch) | |
tree | ebd3eafd0f71a018f51ac34ec10f55e8669c013d /drivers/gpu/nvgpu/gp10b | |
parent | d32bd6605d37f576e186d05e0853120cd9782fd3 (diff) |
gpu: nvgpu: rename hw_chid to chid
hw_chid is a relative id for vgpu. For native it's same as hw id.
Renaming it to chid to avoid confusing.
Jira VFND-3796
Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master/r/1509530
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 16 |
2 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index cfc2eb8d..633fbfb7 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -64,7 +64,7 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c) | |||
64 | addr_hi = u64_hi32(c->userd_iova); | 64 | addr_hi = u64_hi32(c->userd_iova); |
65 | 65 | ||
66 | gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", | 66 | gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", |
67 | c->hw_chid, (u64)c->userd_iova); | 67 | c->chid, (u64)c->userd_iova); |
68 | 68 | ||
69 | nvgpu_mem_wr32(g, &c->inst_block, | 69 | nvgpu_mem_wr32(g, &c->inst_block, |
70 | ram_in_ramfc_w() + ram_fc_userd_w(), | 70 | ram_in_ramfc_w() + ram_fc_userd_w(), |
@@ -134,7 +134,7 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, | |||
134 | gp10b_set_pdb_fault_replay_flags(c->g, mem); | 134 | gp10b_set_pdb_fault_replay_flags(c->g, mem); |
135 | 135 | ||
136 | 136 | ||
137 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); | 137 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); |
138 | 138 | ||
139 | if (c->is_privileged_channel) { | 139 | if (c->is_privileged_channel) { |
140 | /* Set privilege level for channel */ | 140 | /* Set privilege level for channel */ |
@@ -176,7 +176,7 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) | |||
176 | v = pbdma_allowed_syncpoints_0_valid_f(1); | 176 | v = pbdma_allowed_syncpoints_0_valid_f(1); |
177 | 177 | ||
178 | gk20a_dbg_info("Channel %d, syncpt id %d\n", | 178 | gk20a_dbg_info("Channel %d, syncpt id %d\n", |
179 | c->hw_chid, new_syncpt); | 179 | c->chid, new_syncpt); |
180 | 180 | ||
181 | v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); | 181 | v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); |
182 | 182 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 2356f9f3..9ff34325 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1653,7 +1653,7 @@ static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a | |||
1653 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1653 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1654 | "CILP: preempted tsg"); | 1654 | "CILP: preempted tsg"); |
1655 | } else { | 1655 | } else { |
1656 | gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false); | 1656 | gk20a_fifo_issue_preempt(g, fault_ch->chid, false); |
1657 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1657 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1658 | "CILP: preempted channel"); | 1658 | "CILP: preempted channel"); |
1659 | } | 1659 | } |
@@ -1675,7 +1675,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1675 | if (gr_ctx->t18x.cilp_preempt_pending) { | 1675 | if (gr_ctx->t18x.cilp_preempt_pending) { |
1676 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1676 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1677 | "CILP is already pending for chid %d", | 1677 | "CILP is already pending for chid %d", |
1678 | fault_ch->hw_chid); | 1678 | fault_ch->chid); |
1679 | return 0; | 1679 | return 0; |
1680 | } | 1680 | } |
1681 | 1681 | ||
@@ -1718,7 +1718,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1718 | 1718 | ||
1719 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1719 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1720 | "CILP: disabling channel %d", | 1720 | "CILP: disabling channel %d", |
1721 | fault_ch->hw_chid); | 1721 | fault_ch->chid); |
1722 | 1722 | ||
1723 | ret = gr_gp10b_disable_channel_or_tsg(g, fault_ch); | 1723 | ret = gr_gp10b_disable_channel_or_tsg(g, fault_ch); |
1724 | if (ret) { | 1724 | if (ret) { |
@@ -1728,7 +1728,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1728 | 1728 | ||
1729 | /* set cilp_preempt_pending = true and record the channel */ | 1729 | /* set cilp_preempt_pending = true and record the channel */ |
1730 | gr_ctx->t18x.cilp_preempt_pending = true; | 1730 | gr_ctx->t18x.cilp_preempt_pending = true; |
1731 | g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; | 1731 | g->gr.t18x.cilp_preempt_pending_chid = fault_ch->chid; |
1732 | 1732 | ||
1733 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { | 1733 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { |
1734 | struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; | 1734 | struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; |
@@ -1758,7 +1758,7 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, | |||
1758 | if (!gr_ctx->t18x.cilp_preempt_pending) { | 1758 | if (!gr_ctx->t18x.cilp_preempt_pending) { |
1759 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1759 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1760 | "CILP is already cleared for chid %d\n", | 1760 | "CILP is already cleared for chid %d\n", |
1761 | fault_ch->hw_chid); | 1761 | fault_ch->chid); |
1762 | return 0; | 1762 | return 0; |
1763 | } | 1763 | } |
1764 | 1764 | ||
@@ -1879,7 +1879,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) | |||
1879 | 1879 | ||
1880 | chid = g->gr.t18x.cilp_preempt_pending_chid; | 1880 | chid = g->gr.t18x.cilp_preempt_pending_chid; |
1881 | 1881 | ||
1882 | ch = gk20a_channel_get(gk20a_fifo_channel_from_hw_chid(g, chid)); | 1882 | ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid)); |
1883 | if (!ch) | 1883 | if (!ch) |
1884 | return ret; | 1884 | return ret; |
1885 | 1885 | ||
@@ -1923,7 +1923,7 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g, | |||
1923 | goto clean_up; | 1923 | goto clean_up; |
1924 | 1924 | ||
1925 | ch = gk20a_channel_get( | 1925 | ch = gk20a_channel_get( |
1926 | gk20a_fifo_channel_from_hw_chid(g, chid)); | 1926 | gk20a_fifo_channel_from_chid(g, chid)); |
1927 | if (!ch) | 1927 | if (!ch) |
1928 | goto clean_up; | 1928 | goto clean_up; |
1929 | 1929 | ||
@@ -2171,7 +2171,7 @@ static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | |||
2171 | 2171 | ||
2172 | gk20a_dbg(gpu_dbg_sched, "chid=%d tsgid=%d pid=%d " | 2172 | gk20a_dbg(gpu_dbg_sched, "chid=%d tsgid=%d pid=%d " |
2173 | "graphics_preempt=%d compute_preempt=%d", | 2173 | "graphics_preempt=%d compute_preempt=%d", |
2174 | ch->hw_chid, | 2174 | ch->chid, |
2175 | ch->tsgid, | 2175 | ch->tsgid, |
2176 | ch->tgid, | 2176 | ch->tgid, |
2177 | graphics_preempt_mode, | 2177 | graphics_preempt_mode, |