diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-05-23 08:31:43 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-15 08:43:48 -0400 |
commit | 7d16f7e52c0f8ce8604e992a617a3f98545fcf07 (patch) | |
tree | e14b73435e847ddda77b4a72466b6aae44b9ff80 /drivers/gpu/nvgpu/gp10b | |
parent | eb8db3e4df159210ca9c7f834dbbc939a5c67a96 (diff) |
gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>
Remove <soc/tegra/fuse.h> includes and include
<nvgpu/fuse.h> header to remove direct dependency
on platform specific header
Use specific APIs like below to read/write fuses
nvgpu_tegra_fuse_write_bypass()
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable()
Remove old code which was compiled for kernel versions
less than 4.4 since we support only k4.4 and greater
versions now
Jira NVGPU-75
Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 5 |
2 files changed, 8 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9a30ad7c..3bddef4c 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -13,8 +13,6 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <soc/tegra/fuse.h> | ||
17 | |||
18 | #include <dt-bindings/soc/gm20b-fuse.h> | 16 | #include <dt-bindings/soc/gm20b-fuse.h> |
19 | #include <dt-bindings/soc/gp10b-fuse.h> | 17 | #include <dt-bindings/soc/gp10b-fuse.h> |
20 | 18 | ||
@@ -24,6 +22,7 @@ | |||
24 | #include <nvgpu/dma.h> | 22 | #include <nvgpu/dma.h> |
25 | #include <nvgpu/bug.h> | 23 | #include <nvgpu/bug.h> |
26 | #include <nvgpu/debug.h> | 24 | #include <nvgpu/debug.h> |
25 | #include <nvgpu/fuse.h> | ||
27 | 26 | ||
28 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
29 | #include "gk20a/gr_gk20a.h" | 28 | #include "gk20a/gr_gk20a.h" |
@@ -1571,15 +1570,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g) | |||
1571 | 1570 | ||
1572 | static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1571 | static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1573 | { | 1572 | { |
1574 | tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); | 1573 | nvgpu_tegra_fuse_write_bypass(0x1); |
1575 | tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); | 1574 | nvgpu_tegra_fuse_write_access_sw(0x0); |
1576 | 1575 | ||
1577 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) | 1576 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) |
1578 | tegra_fuse_control_write(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1577 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x2); |
1579 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) | 1578 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) |
1580 | tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1579 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); |
1581 | else | 1580 | else |
1582 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1581 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); |
1583 | } | 1582 | } |
1584 | 1583 | ||
1585 | static void gr_gp10b_get_access_map(struct gk20a *g, | 1584 | static void gr_gp10b_get_access_map(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index cd6bf97a..2222cc17 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -13,10 +13,9 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <soc/tegra/fuse.h> | ||
17 | |||
18 | #include <nvgpu/pmu.h> | 16 | #include <nvgpu/pmu.h> |
19 | #include <nvgpu/log.h> | 17 | #include <nvgpu/log.h> |
18 | #include <nvgpu/fuse.h> | ||
20 | 19 | ||
21 | #include "gk20a/gk20a.h" | 20 | #include "gk20a/gk20a.h" |
22 | #include "gk20a/pmu_gk20a.h" | 21 | #include "gk20a/pmu_gk20a.h" |
@@ -383,7 +382,7 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) | |||
383 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 382 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
384 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 383 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", |
385 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 384 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
386 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); | 385 | nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); |
387 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 386 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", |
388 | val); | 387 | val); |
389 | } | 388 | } |