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authorDeepak Nibade <dnibade@nvidia.com>2016-12-27 05:01:00 -0500
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 05:35:06 -0500
commit7a81883a0d70c3a43ad2841ac235f6dc344c60fb (patch)
tree92923d2efccf90d1961071fa9acde59178a0d688 /drivers/gpu/nvgpu/gp10b
parent505b442551a2e27aa3bc9e608c5a2bc9fccecbc4 (diff)
parent2aa3c85f8e82b3c07c39e677663abd3687c1822a (diff)
Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo Bug 200266498 Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/cde_gp10b.c148
-rw-r--r--drivers/gpu/nvgpu/gp10b/cde_gp10b.h23
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce_gp10b.c82
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce_gp10b.h26
-rw-r--r--drivers/gpu/nvgpu/gp10b/fb_gp10b.c108
-rw-r--r--drivers/gpu/nvgpu/gp10b/fb_gp10b.h21
-rw-r--r--drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c53
-rw-r--r--drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h23
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c238
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.h21
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b.c110
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b.h26
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c640
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h93
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c64
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h29
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c73
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h28
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c2257
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h103
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h28
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c269
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.h21
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h217
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h117
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ce_gp10b.h81
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h85
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h473
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h481
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h689
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h181
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h145
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h1277
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h4241
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h581
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h245
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h593
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h205
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pram_gp10b.h57
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h145
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h69
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h165
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h825
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h493
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h409
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h109
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h225
-rw-r--r--drivers/gpu/nvgpu/gp10b/ltc_gp10b.c225
-rw-r--r--drivers/gpu/nvgpu/gp10b/ltc_gp10b.h19
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c202
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.h31
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c417
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.h22
-rw-r--r--drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c751
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.c493
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.h26
-rw-r--r--drivers/gpu/nvgpu/gp10b/regops_gp10b.c511
-rw-r--r--drivers/gpu/nvgpu/gp10b/regops_gp10b.h24
-rw-r--r--drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c150
-rw-r--r--drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h30
-rw-r--r--drivers/gpu/nvgpu/gp10b/therm_gp10b.c130
-rw-r--r--drivers/gpu/nvgpu/gp10b/therm_gp10b.h19
62 files changed, 19642 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.c b/drivers/gpu/nvgpu/gp10b/cde_gp10b.c
new file mode 100644
index 00000000..4a16abd1
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/cde_gp10b.c
@@ -0,0 +1,148 @@
1/*
2 * GP10B CDE
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "cde_gp10b.h"
18
19enum gp10b_programs {
20 GP10B_PROG_HPASS = 0,
21 GP10B_PROG_HPASS_4K = 1,
22 GP10B_PROG_VPASS = 2,
23 GP10B_PROG_VPASS_4K = 3,
24 GP10B_PROG_HPASS_DEBUG = 4,
25 GP10B_PROG_HPASS_4K_DEBUG = 5,
26 GP10B_PROG_VPASS_DEBUG = 6,
27 GP10B_PROG_VPASS_4K_DEBUG = 7,
28 GP10B_PROG_PASSTHROUGH = 8,
29};
30
31static void gp10b_cde_get_program_numbers(struct gk20a *g,
32 u32 block_height_log2,
33 int *hprog_out, int *vprog_out)
34{
35 int hprog, vprog;
36
37 if (g->cde_app.shader_parameter == 1) {
38 hprog = GP10B_PROG_PASSTHROUGH;
39 vprog = GP10B_PROG_PASSTHROUGH;
40 } else {
41 hprog = GP10B_PROG_HPASS;
42 vprog = GP10B_PROG_VPASS;
43 if (g->cde_app.shader_parameter == 2) {
44 hprog = GP10B_PROG_HPASS_DEBUG;
45 vprog = GP10B_PROG_VPASS_DEBUG;
46 }
47 if (g->mm.bypass_smmu) {
48 if (!g->mm.disable_bigpage) {
49 gk20a_warn(g->dev,
50 "when bypass_smmu is 1, disable_bigpage must be 1 too");
51 }
52 hprog |= 1;
53 vprog |= 1;
54 }
55 }
56
57 *hprog_out = hprog;
58 *vprog_out = vprog;
59}
60
61static bool gp10b_need_scatter_buffer(struct gk20a *g)
62{
63 return g->mm.bypass_smmu;
64}
65
66static u8 parity(u32 a)
67{
68 a ^= a>>16u;
69 a ^= a>>8u;
70 a ^= a>>4u;
71 a &= 0xfu;
72 return (0x6996u >> a) & 1u;
73}
74
75static int gp10b_populate_scatter_buffer(struct gk20a *g,
76 struct sg_table *sgt,
77 size_t surface_size,
78 void *scatter_buffer_ptr,
79 size_t scatter_buffer_size)
80{
81 /* map scatter buffer to CPU VA and fill it */
82 const u32 page_size_log2 = 12;
83 const u32 page_size = 1 << page_size_log2;
84 const u32 page_size_shift = page_size_log2 - 7u;
85
86 /* 0011 1111 1111 1111 1111 1110 0100 1000 */
87 const u32 getSliceMaskGP10B = 0x3ffffe48;
88 u8 *scatter_buffer = scatter_buffer_ptr;
89
90 size_t i;
91 struct scatterlist *sg = NULL;
92 u8 d = 0;
93 size_t page = 0;
94 size_t pages_left;
95
96 surface_size = round_up(surface_size, page_size);
97
98 pages_left = surface_size >> page_size_log2;
99 if ((pages_left >> 3) > scatter_buffer_size)
100 return -ENOMEM;
101
102 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
103 unsigned int j;
104 u64 surf_pa = sg_phys(sg);
105 unsigned int n = (int)(sg->length >> page_size_log2);
106
107 gk20a_dbg(gpu_dbg_cde, "surfPA=0x%llx + %d pages", surf_pa, n);
108
109 for (j=0; j < n && pages_left > 0; j++, surf_pa += page_size) {
110 u32 addr = (((u32)(surf_pa>>7)) & getSliceMaskGP10B) >> page_size_shift;
111 u8 scatter_bit = parity(addr);
112 u8 bit = page & 7;
113
114 d |= scatter_bit << bit;
115 if (bit == 7) {
116 scatter_buffer[page >> 3] = d;
117 d = 0;
118 }
119
120 ++page;
121 --pages_left;
122 }
123
124 if (pages_left == 0)
125 break;
126 }
127
128 /* write the last byte in case the number of pages is not divisible by 8 */
129 if ((page & 7) != 0)
130 scatter_buffer[page >> 3] = d;
131
132#if defined(GK20A_DEBUG)
133 if (unlikely(gpu_dbg_cde & gk20a_dbg_mask)) {
134 gk20a_dbg(gpu_dbg_cde, "scatterBuffer content:");
135 for (i=0; i < page>>3; i++) {
136 gk20a_dbg(gpu_dbg_cde, " %x", scatter_buffer[i]);
137 }
138 }
139#endif
140 return 0;
141}
142
143void gp10b_init_cde_ops(struct gpu_ops *gops)
144{
145 gops->cde.get_program_numbers = gp10b_cde_get_program_numbers;
146 gops->cde.need_scatter_buffer = gp10b_need_scatter_buffer;
147 gops->cde.populate_scatter_buffer = gp10b_populate_scatter_buffer;
148}
diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.h b/drivers/gpu/nvgpu/gp10b/cde_gp10b.h
new file mode 100644
index 00000000..52f785f1
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/cde_gp10b.h
@@ -0,0 +1,23 @@
1/*
2 * GP10B CDE
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVHOST_GP10B_CDE
17#define _NVHOST_GP10B_CDE
18
19struct gpu_ops;
20
21void gp10b_init_cde_ops(struct gpu_ops *gops);
22
23#endif
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
new file mode 100644
index 00000000..e5082778
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c
@@ -0,0 +1,82 @@
1/*
2 * Pascal GPU series Copy Engine.
3 *
4 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.
17 */
18
19#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
20#include "hw_ce_gp10b.h"
21#include "ce_gp10b.h"
22
23static void ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
24{
25 gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n");
26
27 /* wake theads waiting in this channel */
28 gk20a_channel_semaphore_wakeup(g, true);
29 return;
30}
31
32static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
33{
34 gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n");
35
36 return ce_intr_status_blockpipe_pending_f();
37}
38
39static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr)
40{
41 gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n");
42
43 return ce_intr_status_launcherr_pending_f();
44}
45
46static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
47{
48 u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
49 u32 clear_intr = 0;
50
51 gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
52
53 /* clear blocking interrupts: they exibit broken behavior */
54 if (ce_intr & ce_intr_status_blockpipe_pending_f())
55 clear_intr |= ce_blockpipe_isr(g, ce_intr);
56
57 if (ce_intr & ce_intr_status_launcherr_pending_f())
58 clear_intr |= ce_launcherr_isr(g, ce_intr);
59
60 gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
61 return;
62}
63
64static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
65{
66 u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
67
68 gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
69
70 if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) {
71 gk20a_writel(g, ce_intr_status_r(inst_id),
72 ce_intr_status_nonblockpipe_pending_f());
73 ce_nonblockpipe_isr(g, ce_intr);
74 }
75
76 return;
77}
78void gp10b_init_ce(struct gpu_ops *gops)
79{
80 gops->ce2.isr_stall = gp10b_ce_isr;
81 gops->ce2.isr_nonstall = gp10b_ce_nonstall_isr;
82}
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
new file mode 100644
index 00000000..948d0454
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h
@@ -0,0 +1,26 @@
1/*
2 * Pascal GPU series Copy Engine.
3 *
4 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.
17 */
18#ifndef __CE_GP10B_H__
19#define __CE_GP10B_H__
20
21#include "gk20a/channel_gk20a.h"
22#include "gk20a/tsg_gk20a.h"
23
24void gp10b_init_ce(struct gpu_ops *gops);
25
26#endif /*__CE2_GP10B_H__*/
diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c
new file mode 100644
index 00000000..5324b5ef
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c
@@ -0,0 +1,108 @@
1/*
2 * GP10B FB
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5*
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17
18#include "gk20a/gk20a.h"
19#include "gm20b/fb_gm20b.h"
20#include "gk20a/kind_gk20a.h"
21
22#include "hw_gmmu_gp10b.h"
23
24static void gp10b_init_uncompressed_kind_map(void)
25{
26 gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] =
27 gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] =
28 gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] =
29 gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] =
30 gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] =
31 gmmu_pte_kind_z16_v();
32
33 gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] =
34 gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] =
35 gmmu_pte_kind_generic_16bx2_v();
36}
37
38static bool gp10b_kind_supported(u8 k)
39{
40 return (k >= gmmu_pte_kind_z16_2cz_v() &&
41 k <= gmmu_pte_kind_z16_ms8_2cz_v())
42 || k == gmmu_pte_kind_z16_ms16_2cz_v()
43 || k == gmmu_pte_kind_c32_ms4_4cbra_v()
44 || k == gmmu_pte_kind_c64_ms4_4cbra_v();
45}
46
47static bool gp10b_kind_z(u8 k)
48{
49 return (k >= gmmu_pte_kind_z16_2cz_v() &&
50 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
51 k == gmmu_pte_kind_z16_ms16_2cz_v();
52}
53
54static bool gp10b_kind_compressible(u8 k)
55{
56 return (k >= gmmu_pte_kind_z16_2cz_v() &&
57 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
58 k == gmmu_pte_kind_z16_ms16_2cz_v() ||
59 (k >= gmmu_pte_kind_z16_4cz_v() &&
60 k <= gmmu_pte_kind_z16_ms16_4cz_v()) ||
61 k == gmmu_pte_kind_c32_ms4_4cbra_v() ||
62 k == gmmu_pte_kind_c64_ms4_4cbra_v();
63}
64
65static bool gp10b_kind_zbc(u8 k)
66{
67 return (k >= gmmu_pte_kind_z16_2cz_v() &&
68 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
69 k == gmmu_pte_kind_z16_ms16_2cz_v() ||
70 k == gmmu_pte_kind_c32_ms4_4cbra_v() ||
71 k == gmmu_pte_kind_c64_ms4_4cbra_v();
72}
73
74static void gp10b_init_kind_attr(void)
75{
76 u16 k;
77
78 for (k = 0; k < 256; k++) {
79 if (gp10b_kind_supported((u8)k))
80 gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED;
81 if (gp10b_kind_compressible((u8)k))
82 gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE;
83 if (gp10b_kind_z((u8)k))
84 gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z;
85 if (gp10b_kind_zbc((u8)k))
86 gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC;
87 }
88}
89
90static unsigned int gp10b_fb_compression_page_size(struct gk20a *g)
91{
92 return SZ_64K;
93}
94
95static unsigned int gp10b_fb_compressible_page_size(struct gk20a *g)
96{
97 return SZ_4K;
98}
99
100void gp10b_init_fb(struct gpu_ops *gops)
101{
102 gm20b_init_fb(gops);
103 gops->fb.compression_page_size = gp10b_fb_compression_page_size;
104 gops->fb.compressible_page_size = gp10b_fb_compressible_page_size;
105
106 gp10b_init_uncompressed_kind_map();
107 gp10b_init_kind_attr();
108}
diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/fb_gp10b.h
new file mode 100644
index 00000000..76efd331
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.h
@@ -0,0 +1,21 @@
1/*
2 * GP10B FB
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_GP10B_FB
17#define _NVGPU_GP10B_FB
18struct gpu_ops;
19
20void gp10b_init_fb(struct gpu_ops *gops);
21#endif
diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c
new file mode 100644
index 00000000..7dd200a9
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c
@@ -0,0 +1,53 @@
1/*
2 * GP10B GPU FECS traces
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "gk20a/fecs_trace_gk20a.h"
18#include "gp10b/hw_ctxsw_prog_gp10b.h"
19#include "gp10b/hw_gr_gp10b.h"
20
21#ifdef CONFIG_GK20A_CTXSW_TRACE
22static int gp10b_fecs_trace_flush(struct gk20a *g)
23{
24 struct fecs_method_op_gk20a op = {
25 .mailbox = { .id = 0, .data = 0,
26 .clr = ~0, .ok = 0, .fail = 0},
27 .method.addr = gr_fecs_method_push_adr_write_timestamp_record_v(),
28 .method.data = 0,
29 .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL,
30 .cond.fail = GR_IS_UCODE_OP_SKIP,
31 };
32 int err;
33
34 gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "");
35
36 err = gr_gk20a_elpg_protected_call(g,
37 gr_gk20a_submit_fecs_method_op(g, op, false));
38 if (err)
39 gk20a_err(dev_from_gk20a(g), "write timestamp record failed");
40
41 return err;
42}
43
44void gp10b_init_fecs_trace_ops(struct gpu_ops *ops)
45{
46 gk20a_init_fecs_trace_ops(ops);
47 ops->fecs_trace.flush = gp10b_fecs_trace_flush;
48}
49#else
50void gp10b_init_fecs_trace_ops(struct gpu_ops *ops)
51{
52}
53#endif /* CONFIG_GK20A_CTXSW_TRACE */
diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
new file mode 100644
index 00000000..2a25f4f6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
@@ -0,0 +1,23 @@
1/*
2 * GP10B GPU FECS traces
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_FECS_TRACE_GP10B_H_
17#define _NVGPU_FECS_TRACE_GP10B_H_
18
19struct gpu_ops;
20
21int gp10b_init_fecs_trace_ops(struct gpu_ops *);
22
23#endif
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
new file mode 100644
index 00000000..40bfa2a5
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -0,0 +1,238 @@
1/*
2 * GP10B fifo
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/delay.h>
17#include <linux/types.h>
18
19#include "gk20a/gk20a.h"
20#include "gm20b/fifo_gm20b.h"
21#include "hw_pbdma_gp10b.h"
22#include "fifo_gp10b.h"
23#include "hw_ccsr_gp10b.h"
24#include "hw_fifo_gp10b.h"
25#include "hw_ram_gp10b.h"
26#include "hw_top_gp10b.h"
27
28static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g,
29 struct mem_desc *mem)
30{
31 u32 val;
32
33 gk20a_dbg_fn("");
34
35 val = gk20a_mem_rd32(g, mem,
36 ram_in_page_dir_base_fault_replay_tex_w());
37 val &= ~ram_in_page_dir_base_fault_replay_tex_m();
38 val |= ram_in_page_dir_base_fault_replay_tex_true_f();
39 gk20a_mem_wr32(g, mem,
40 ram_in_page_dir_base_fault_replay_tex_w(), val);
41
42 val = gk20a_mem_rd32(g, mem,
43 ram_in_page_dir_base_fault_replay_gcc_w());
44 val &= ~ram_in_page_dir_base_fault_replay_gcc_m();
45 val |= ram_in_page_dir_base_fault_replay_gcc_true_f();
46 gk20a_mem_wr32(g, mem,
47 ram_in_page_dir_base_fault_replay_gcc_w(), val);
48
49 gk20a_dbg_fn("done");
50}
51
52int channel_gp10b_commit_userd(struct channel_gk20a *c)
53{
54 u32 addr_lo;
55 u32 addr_hi;
56 struct gk20a *g = c->g;
57
58 gk20a_dbg_fn("");
59
60 addr_lo = u64_lo32(c->userd_iova >> ram_userd_base_shift_v());
61 addr_hi = u64_hi32(c->userd_iova);
62
63 gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx",
64 c->hw_chid, (u64)c->userd_iova);
65
66 gk20a_mem_wr32(g, &c->inst_block,
67 ram_in_ramfc_w() + ram_fc_userd_w(),
68 (g->mm.vidmem_is_vidmem ?
69 pbdma_userd_target_sys_mem_ncoh_f() :
70 pbdma_userd_target_vid_mem_f()) |
71 pbdma_userd_addr_f(addr_lo));
72
73 gk20a_mem_wr32(g, &c->inst_block,
74 ram_in_ramfc_w() + ram_fc_userd_hi_w(),
75 pbdma_userd_hi_addr_f(addr_hi));
76
77 return 0;
78}
79
80static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
81 u64 gpfifo_base, u32 gpfifo_entries, u32 flags)
82{
83 struct gk20a *g = c->g;
84 struct mem_desc *mem = &c->inst_block;
85
86 gk20a_dbg_fn("");
87
88 gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v());
89
90 gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(),
91 pbdma_gp_base_offset_f(
92 u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
93
94 gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
95 pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
96 pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
97
98 gk20a_mem_wr32(g, mem, ram_fc_signature_w(),
99 c->g->ops.fifo.get_pbdma_signature(c->g));
100
101 gk20a_mem_wr32(g, mem, ram_fc_formats_w(),
102 pbdma_formats_gp_fermi0_f() |
103 pbdma_formats_pb_fermi1_f() |
104 pbdma_formats_mp_fermi0_f());
105
106 gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(),
107 pbdma_pb_header_priv_user_f() |
108 pbdma_pb_header_method_zero_f() |
109 pbdma_pb_header_subchannel_zero_f() |
110 pbdma_pb_header_level_main_f() |
111 pbdma_pb_header_first_true_f() |
112 pbdma_pb_header_type_inc_f());
113
114 gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(),
115 pbdma_subdevice_id_f(1) |
116 pbdma_subdevice_status_active_f() |
117 pbdma_subdevice_channel_dma_enable_f());
118
119 gk20a_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f());
120
121 gk20a_mem_wr32(g, mem, ram_fc_acquire_w(),
122 channel_gk20a_pbdma_acquire_val(c));
123
124 gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
125 pbdma_runlist_timeslice_timeout_128_f() |
126 pbdma_runlist_timeslice_timescale_3_f() |
127 pbdma_runlist_timeslice_enable_true_f());
128
129 if ( flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE)
130 gp10b_set_pdb_fault_replay_flags(c->g, mem);
131
132
133 gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
134
135 if (c->is_privileged_channel) {
136 /* Set privilege level for channel */
137 gk20a_mem_wr32(g, mem, ram_fc_config_w(),
138 pbdma_config_auth_level_privileged_f());
139
140 gk20a_channel_setup_ramfc_for_privileged_channel(c);
141 }
142
143 return channel_gp10b_commit_userd(c);
144}
145
146static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g)
147{
148 return g->gpu_characteristics.gpfifo_class
149 | pbdma_signature_sw_zero_f();
150}
151
152static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
153{
154 u32 new_syncpt = 0, old_syncpt;
155 u32 v;
156
157 gk20a_dbg_fn("");
158
159 v = gk20a_mem_rd32(c->g, &c->inst_block,
160 ram_fc_allowed_syncpoints_w());
161 old_syncpt = pbdma_allowed_syncpoints_0_index_v(v);
162 if (c->sync)
163 new_syncpt = c->sync->syncpt_id(c->sync);
164
165 if (new_syncpt && new_syncpt != old_syncpt) {
166 /* disable channel */
167 gk20a_disable_channel_tsg(c->g, c);
168
169 /* preempt the channel */
170 WARN_ON(gk20a_fifo_preempt(c->g, c));
171
172 v = pbdma_allowed_syncpoints_0_valid_f(1);
173
174 gk20a_dbg_info("Channel %d, syncpt id %d\n",
175 c->hw_chid, new_syncpt);
176
177 v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt);
178
179 gk20a_mem_wr32(c->g, &c->inst_block,
180 ram_fc_allowed_syncpoints_w(), v);
181 }
182
183 /* enable channel */
184 gk20a_enable_channel_tsg(c->g, c);
185
186 gk20a_dbg_fn("done");
187
188 return 0;
189}
190
191static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
192 u32 *inst_id)
193{
194 int ret = ENGINE_INVAL_GK20A;
195
196 gk20a_dbg_info("engine type %d", engine_type);
197 if (engine_type == top_device_info_type_enum_graphics_v())
198 ret = ENGINE_GR_GK20A;
199 else if (engine_type == top_device_info_type_enum_lce_v()) {
200 /* Default assumptions - all the CE engine have separate runlist */
201 ret = ENGINE_ASYNC_CE_GK20A;
202 }
203
204 return ret;
205}
206
207static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
208 u32 *inst_id, u32 *pri_base, u32 *fault_id)
209{
210 if (top_device_info_data_type_v(table_entry) ==
211 top_device_info_data_type_enum2_v()) {
212 if (inst_id)
213 *inst_id = top_device_info_data_inst_id_v(table_entry);
214 if (pri_base) {
215 *pri_base =
216 (top_device_info_data_pri_base_v(table_entry)
217 << top_device_info_data_pri_base_align_v());
218 }
219 if (fault_id && (top_device_info_data_fault_id_v(table_entry) ==
220 top_device_info_data_fault_id_valid_v())) {
221 *fault_id =
222 top_device_info_data_fault_id_enum_v(table_entry);
223 }
224 } else
225 gk20a_err(g->dev, "unknown device_info_data %d",
226 top_device_info_data_type_v(table_entry));
227}
228
229void gp10b_init_fifo(struct gpu_ops *gops)
230{
231 gm20b_init_fifo(gops);
232 gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc;
233 gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature;
234 gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
235 gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
236 gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
237 gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
238}
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
new file mode 100644
index 00000000..3ef8247f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
@@ -0,0 +1,21 @@
1/*
2 * GP10B Fifo
3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef FIFO_GP10B_H
17#define FIFO_GP10B_H
18struct gpu_ops;
19void gp10b_init_fifo(struct gpu_ops *gops);
20int channel_gp10b_commit_userd(struct channel_gk20a *c);
21#endif
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c
new file mode 100644
index 00000000..a541dda3
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b.c
@@ -0,0 +1,110 @@
1/*
2 * GP10B Graphics
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "gk20a/gk20a.h"
20#include "hw_fuse_gp10b.h"
21#include "hw_gr_gp10b.h"
22
23static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
24{
25 u64 ecc_enabled_units = 0;
26 u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
27 u32 opt_feature_fuses_override_disable =
28 gk20a_readl(g,
29 fuse_opt_feature_fuses_override_disable_r());
30 u32 fecs_feature_override_ecc =
31 gk20a_readl(g,
32 gr_fecs_feature_override_ecc_r());
33
34 if (opt_feature_fuses_override_disable) {
35 if (opt_ecc_en)
36 ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED;
37 else
38 ecc_enabled_units = 0;
39 } else {
40 /* SM LRF */
41 if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
42 fecs_feature_override_ecc)) {
43 if (gr_fecs_feature_override_ecc_sm_lrf_v(
44 fecs_feature_override_ecc)) {
45 ecc_enabled_units |=
46 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
47 }
48 } else {
49 if (opt_ecc_en) {
50 ecc_enabled_units |=
51 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
52 }
53 }
54
55 /* SM SHM */
56 if (gr_fecs_feature_override_ecc_sm_shm_override_v(
57 fecs_feature_override_ecc)) {
58 if (gr_fecs_feature_override_ecc_sm_shm_v(
59 fecs_feature_override_ecc)) {
60 ecc_enabled_units |=
61 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
62 }
63 } else {
64 if (opt_ecc_en) {
65 ecc_enabled_units |=
66 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
67 }
68 }
69
70 /* TEX */
71 if (gr_fecs_feature_override_ecc_tex_override_v(
72 fecs_feature_override_ecc)) {
73 if (gr_fecs_feature_override_ecc_tex_v(
74 fecs_feature_override_ecc)) {
75 ecc_enabled_units |=
76 NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
77 }
78 } else {
79 if (opt_ecc_en) {
80 ecc_enabled_units |=
81 NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
82 }
83 }
84
85 /* LTC */
86 if (gr_fecs_feature_override_ecc_ltc_override_v(
87 fecs_feature_override_ecc)) {
88 if (gr_fecs_feature_override_ecc_ltc_v(
89 fecs_feature_override_ecc)) {
90 ecc_enabled_units |=
91 NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
92 }
93 } else {
94 if (opt_ecc_en) {
95 ecc_enabled_units |=
96 NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
97 }
98 }
99 }
100
101 return ecc_enabled_units;
102}
103
104int gp10b_init_gpu_characteristics(struct gk20a *g)
105{
106 gk20a_init_gpu_characteristics(g);
107 g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g);
108
109 return 0;
110}
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.h b/drivers/gpu/nvgpu/gp10b/gp10b.h
new file mode 100644
index 00000000..263f3cbe
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b.h
@@ -0,0 +1,26 @@
1/*
2 * GP10B Graphics
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef GP10B_H
20#define GP10B_H
21
22#include "gk20a/gk20a.h"
23
24int gp10b_init_gpu_characteristics(struct gk20a *g);
25
26#endif /* GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c
new file mode 100644
index 00000000..563819de
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c
@@ -0,0 +1,640 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
16 *
17 * This file is autogenerated. Do not edit.
18 */
19
20#ifndef __gp10b_gating_reglist_h__
21#define __gp10b_gating_reglist_h__
22
23#include <linux/types.h>
24#include "gp10b_gating_reglist.h"
25
26struct gating_desc {
27 u32 addr;
28 u32 prod;
29 u32 disable;
30};
31/* slcg bus */
32static const struct gating_desc gp10b_slcg_bus[] = {
33 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
34};
35
36/* slcg ce2 */
37static const struct gating_desc gp10b_slcg_ce2[] = {
38 {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
39};
40
41/* slcg chiplet */
42static const struct gating_desc gp10b_slcg_chiplet[] = {
43 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
44 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
45 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
46 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
47};
48
49/* slcg fb */
50static const struct gating_desc gp10b_slcg_fb[] = {
51 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
52 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
53};
54
55/* slcg fifo */
56static const struct gating_desc gp10b_slcg_fifo[] = {
57 {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe},
58};
59
60/* slcg gr */
61static const struct gating_desc gp10b_slcg_gr[] = {
62 {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe},
63 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
64 {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
65 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
66 {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe},
67 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
68 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
69 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
70 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
71 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
72 {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
73 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
74 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
75 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
76 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e},
77 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
78 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
79 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
80 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
81 {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe},
82 {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe},
83 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
84 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
85 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
86 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
87 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
88 {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
89 {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
90 {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
91 {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
92 {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
93 {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
94 {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
95 {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
96 {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
97 {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
98 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
99 {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
100 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
101 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
102 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
103 {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
104 {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
105 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
106 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
107 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
108 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
109 {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
110 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
111 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
112 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
113 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
114};
115
116/* slcg ltc */
117static const struct gating_desc gp10b_slcg_ltc[] = {
118 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
119 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
120};
121
122/* slcg perf */
123static const struct gating_desc gp10b_slcg_perf[] = {
124 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
125 {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
126 {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
127 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
128};
129
130/* slcg PriRing */
131static const struct gating_desc gp10b_slcg_priring[] = {
132 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
133};
134
135/* slcg pwr_csb */
136static const struct gating_desc gp10b_slcg_pwr_csb[] = {
137 {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe},
138 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
139 {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe},
140 {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f},
141};
142
143/* slcg pmu */
144static const struct gating_desc gp10b_slcg_pmu[] = {
145 {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
146 {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe},
147 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
148};
149
150/* therm gr */
151static const struct gating_desc gp10b_slcg_therm[] = {
152 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
153};
154
155/* slcg Xbar */
156static const struct gating_desc gp10b_slcg_xbar[] = {
157 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
158 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
159};
160
161/* blcg bus */
162static const struct gating_desc gp10b_blcg_bus[] = {
163 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
164};
165
166/* blcg ce */
167static const struct gating_desc gp10b_blcg_ce[] = {
168 {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000},
169};
170
171/* blcg ctxsw prog */
172static const struct gating_desc gp10b_blcg_ctxsw_prog[] = {
173};
174
175/* blcg fb */
176static const struct gating_desc gp10b_blcg_fb[] = {
177 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
178 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
179 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
180 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
181 {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
182};
183
184/* blcg fifo */
185static const struct gating_desc gp10b_blcg_fifo[] = {
186 {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
187};
188
189/* blcg gr */
190static const struct gating_desc gp10b_blcg_gr[] = {
191 {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
192 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
193 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
194 {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
195 {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
196 {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
197 {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
198 {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
199 {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
200 {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
201 {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
202 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
203 {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
204 {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
205 {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
206 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
207 {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
208 {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
209 {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
210 {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
211 {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
212 {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
213 {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
214 {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
215 {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
216 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
217 {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
218 {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
219 {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
220 {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
221 {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
222 {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
223 {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
224 {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
225 {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
226 {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
227 {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
228 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
229 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
230 {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
231 {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
232 {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
233 {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
234 {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
235 {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
236 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
237 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
238 {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
239 {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
240 {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
241 {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
242 {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
243 {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
244};
245
246/* blcg ltc */
247static const struct gating_desc gp10b_blcg_ltc[] = {
248 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
249 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
250 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
251 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
252};
253
254/* blcg pwr_csb */
255static const struct gating_desc gp10b_blcg_pwr_csb[] = {
256 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
257};
258
259/* blcg pmu */
260static const struct gating_desc gp10b_blcg_pmu[] = {
261 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
262};
263
264/* blcg Xbar */
265static const struct gating_desc gp10b_blcg_xbar[] = {
266 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
267 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
268};
269
270/* pg gr */
271static const struct gating_desc gp10b_pg_gr[] = {
272};
273
274/* inline functions */
275void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
276 bool prod)
277{
278 u32 i;
279 u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc);
280 for (i = 0; i < size; i++) {
281 if (prod)
282 gk20a_writel(g, gp10b_slcg_bus[i].addr,
283 gp10b_slcg_bus[i].prod);
284 else
285 gk20a_writel(g, gp10b_slcg_bus[i].addr,
286 gp10b_slcg_bus[i].disable);
287 }
288}
289
290void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
291 bool prod)
292{
293 u32 i;
294 u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc);
295 for (i = 0; i < size; i++) {
296 if (prod)
297 gk20a_writel(g, gp10b_slcg_ce2[i].addr,
298 gp10b_slcg_ce2[i].prod);
299 else
300 gk20a_writel(g, gp10b_slcg_ce2[i].addr,
301 gp10b_slcg_ce2[i].disable);
302 }
303}
304
305void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
306 bool prod)
307{
308 u32 i;
309 u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc);
310 for (i = 0; i < size; i++) {
311 if (prod)
312 gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
313 gp10b_slcg_chiplet[i].prod);
314 else
315 gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
316 gp10b_slcg_chiplet[i].disable);
317 }
318}
319
320void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
321 bool prod)
322{
323}
324
325void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
326 bool prod)
327{
328 u32 i;
329 u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc);
330 for (i = 0; i < size; i++) {
331 if (prod)
332 gk20a_writel(g, gp10b_slcg_fb[i].addr,
333 gp10b_slcg_fb[i].prod);
334 else
335 gk20a_writel(g, gp10b_slcg_fb[i].addr,
336 gp10b_slcg_fb[i].disable);
337 }
338}
339
340void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
341 bool prod)
342{
343 u32 i;
344 u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc);
345 for (i = 0; i < size; i++) {
346 if (prod)
347 gk20a_writel(g, gp10b_slcg_fifo[i].addr,
348 gp10b_slcg_fifo[i].prod);
349 else
350 gk20a_writel(g, gp10b_slcg_fifo[i].addr,
351 gp10b_slcg_fifo[i].disable);
352 }
353}
354
355void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
356 bool prod)
357{
358 u32 i;
359 u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc);
360 for (i = 0; i < size; i++) {
361 if (prod)
362 gk20a_writel(g, gp10b_slcg_gr[i].addr,
363 gp10b_slcg_gr[i].prod);
364 else
365 gk20a_writel(g, gp10b_slcg_gr[i].addr,
366 gp10b_slcg_gr[i].disable);
367 }
368}
369
370void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
371 bool prod)
372{
373 u32 i;
374 u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc);
375 for (i = 0; i < size; i++) {
376 if (prod)
377 gk20a_writel(g, gp10b_slcg_ltc[i].addr,
378 gp10b_slcg_ltc[i].prod);
379 else
380 gk20a_writel(g, gp10b_slcg_ltc[i].addr,
381 gp10b_slcg_ltc[i].disable);
382 }
383}
384
385void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
386 bool prod)
387{
388 u32 i;
389 u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc);
390 for (i = 0; i < size; i++) {
391 if (prod)
392 gk20a_writel(g, gp10b_slcg_perf[i].addr,
393 gp10b_slcg_perf[i].prod);
394 else
395 gk20a_writel(g, gp10b_slcg_perf[i].addr,
396 gp10b_slcg_perf[i].disable);
397 }
398}
399
400void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
401 bool prod)
402{
403 u32 i;
404 u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc);
405 for (i = 0; i < size; i++) {
406 if (prod)
407 gk20a_writel(g, gp10b_slcg_priring[i].addr,
408 gp10b_slcg_priring[i].prod);
409 else
410 gk20a_writel(g, gp10b_slcg_priring[i].addr,
411 gp10b_slcg_priring[i].disable);
412 }
413}
414
415void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
416 bool prod)
417{
418 u32 i;
419 u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc);
420 for (i = 0; i < size; i++) {
421 if (prod)
422 gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
423 gp10b_slcg_pwr_csb[i].prod);
424 else
425 gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
426 gp10b_slcg_pwr_csb[i].disable);
427 }
428}
429
430void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
431 bool prod)
432{
433 u32 i;
434 u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc);
435 for (i = 0; i < size; i++) {
436 if (prod)
437 gk20a_writel(g, gp10b_slcg_pmu[i].addr,
438 gp10b_slcg_pmu[i].prod);
439 else
440 gk20a_writel(g, gp10b_slcg_pmu[i].addr,
441 gp10b_slcg_pmu[i].disable);
442 }
443}
444
445void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
446 bool prod)
447{
448 u32 i;
449 u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc);
450 for (i = 0; i < size; i++) {
451 if (prod)
452 gk20a_writel(g, gp10b_slcg_therm[i].addr,
453 gp10b_slcg_therm[i].prod);
454 else
455 gk20a_writel(g, gp10b_slcg_therm[i].addr,
456 gp10b_slcg_therm[i].disable);
457 }
458}
459
460void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
461 bool prod)
462{
463 u32 i;
464 u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc);
465 for (i = 0; i < size; i++) {
466 if (prod)
467 gk20a_writel(g, gp10b_slcg_xbar[i].addr,
468 gp10b_slcg_xbar[i].prod);
469 else
470 gk20a_writel(g, gp10b_slcg_xbar[i].addr,
471 gp10b_slcg_xbar[i].disable);
472 }
473}
474
475void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
476 bool prod)
477{
478 u32 i;
479 u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc);
480 for (i = 0; i < size; i++) {
481 if (prod)
482 gk20a_writel(g, gp10b_blcg_bus[i].addr,
483 gp10b_blcg_bus[i].prod);
484 else
485 gk20a_writel(g, gp10b_blcg_bus[i].addr,
486 gp10b_blcg_bus[i].disable);
487 }
488}
489
490void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
491 bool prod)
492{
493 u32 i;
494 u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc);
495 for (i = 0; i < size; i++) {
496 if (prod)
497 gk20a_writel(g, gp10b_blcg_ce[i].addr,
498 gp10b_blcg_ce[i].prod);
499 else
500 gk20a_writel(g, gp10b_blcg_ce[i].addr,
501 gp10b_blcg_ce[i].disable);
502 }
503}
504
505void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
506 bool prod)
507{
508 u32 i;
509 u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc);
510 for (i = 0; i < size; i++) {
511 if (prod)
512 gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
513 gp10b_blcg_ctxsw_prog[i].prod);
514 else
515 gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
516 gp10b_blcg_ctxsw_prog[i].disable);
517 }
518}
519
520void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
521 bool prod)
522{
523 u32 i;
524 u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc);
525 for (i = 0; i < size; i++) {
526 if (prod)
527 gk20a_writel(g, gp10b_blcg_fb[i].addr,
528 gp10b_blcg_fb[i].prod);
529 else
530 gk20a_writel(g, gp10b_blcg_fb[i].addr,
531 gp10b_blcg_fb[i].disable);
532 }
533}
534
535void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
536 bool prod)
537{
538 u32 i;
539 u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc);
540 for (i = 0; i < size; i++) {
541 if (prod)
542 gk20a_writel(g, gp10b_blcg_fifo[i].addr,
543 gp10b_blcg_fifo[i].prod);
544 else
545 gk20a_writel(g, gp10b_blcg_fifo[i].addr,
546 gp10b_blcg_fifo[i].disable);
547 }
548}
549
550void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
551 bool prod)
552{
553 u32 i;
554 u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc);
555 for (i = 0; i < size; i++) {
556 if (prod)
557 gk20a_writel(g, gp10b_blcg_gr[i].addr,
558 gp10b_blcg_gr[i].prod);
559 else
560 gk20a_writel(g, gp10b_blcg_gr[i].addr,
561 gp10b_blcg_gr[i].disable);
562 }
563}
564
565void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
566 bool prod)
567{
568 u32 i;
569 u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc);
570 for (i = 0; i < size; i++) {
571 if (prod)
572 gk20a_writel(g, gp10b_blcg_ltc[i].addr,
573 gp10b_blcg_ltc[i].prod);
574 else
575 gk20a_writel(g, gp10b_blcg_ltc[i].addr,
576 gp10b_blcg_ltc[i].disable);
577 }
578}
579
580void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
581 bool prod)
582{
583 u32 i;
584 u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc);
585 for (i = 0; i < size; i++) {
586 if (prod)
587 gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
588 gp10b_blcg_pwr_csb[i].prod);
589 else
590 gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
591 gp10b_blcg_pwr_csb[i].disable);
592 }
593}
594
595void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
596 bool prod)
597{
598 u32 i;
599 u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc);
600 for (i = 0; i < size; i++) {
601 if (prod)
602 gk20a_writel(g, gp10b_blcg_pmu[i].addr,
603 gp10b_blcg_pmu[i].prod);
604 else
605 gk20a_writel(g, gp10b_blcg_pmu[i].addr,
606 gp10b_blcg_pmu[i].disable);
607 }
608}
609
610void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
611 bool prod)
612{
613 u32 i;
614 u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc);
615 for (i = 0; i < size; i++) {
616 if (prod)
617 gk20a_writel(g, gp10b_blcg_xbar[i].addr,
618 gp10b_blcg_xbar[i].prod);
619 else
620 gk20a_writel(g, gp10b_blcg_xbar[i].addr,
621 gp10b_blcg_xbar[i].disable);
622 }
623}
624
625void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
626 bool prod)
627{
628 u32 i;
629 u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc);
630 for (i = 0; i < size; i++) {
631 if (prod)
632 gk20a_writel(g, gp10b_pg_gr[i].addr,
633 gp10b_pg_gr[i].prod);
634 else
635 gk20a_writel(g, gp10b_pg_gr[i].addr,
636 gp10b_pg_gr[i].disable);
637 }
638}
639
640#endif /* __gp10b_gating_reglist_h__ */
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h
new file mode 100644
index 00000000..e4080def
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h
@@ -0,0 +1,93 @@
1/*
2 * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18
19void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
20 bool prod);
21
22void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
23 bool prod);
24
25void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
26 bool prod);
27
28void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
29 bool prod);
30
31void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
32 bool prod);
33
34void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
35 bool prod);
36
37void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
38 bool prod);
39
40void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
41 bool prod);
42
43void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
44 bool prod);
45
46void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
47 bool prod);
48
49void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
50 bool prod);
51
52void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
53 bool prod);
54
55void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
56 bool prod);
57
58void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
59 bool prod);
60
61void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
62 bool prod);
63
64void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
65 bool prod);
66
67void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
68 bool prod);
69
70void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
71 bool prod);
72
73void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
74 bool prod);
75
76void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
77 bool prod);
78
79void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
80 bool prod);
81
82void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
83 bool prod);
84
85void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
86 bool prod);
87
88void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
89 bool prod);
90
91void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
92 bool prod);
93
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c
new file mode 100644
index 00000000..5035bb99
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c
@@ -0,0 +1,64 @@
1/*
2 * GP10B specific sysfs files
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/platform_device.h>
17
18#include "gk20a/gk20a.h"
19#include "gp10b_sysfs.h"
20
21#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH)
22
23static ssize_t ecc_enable_store(struct device *dev,
24 struct device_attribute *attr, const char *buf, size_t count)
25{
26 struct gk20a *g = get_gk20a(dev);
27 u32 ecc_mask;
28 u32 err = 0;
29
30 err = sscanf(buf, "%d", &ecc_mask);
31 if (err == 1) {
32 err = g->ops.pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd
33 (g, ecc_mask);
34 if (err)
35 dev_err(dev, "ECC override did not happen\n");
36 } else
37 return -EINVAL;
38 return count;
39}
40
41static ssize_t ecc_enable_read(struct device *dev,
42 struct device_attribute *attr, char *buf)
43{
44 struct gk20a *g = get_gk20a(dev);
45
46 return sprintf(buf, "ecc override =0x%x\n",
47 g->ops.gr.get_lrf_tex_ltc_dram_override(g));
48}
49
50static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store);
51
52void gp10b_create_sysfs(struct device *dev)
53{
54 int error = 0;
55
56 error |= device_create_file(dev, &dev_attr_ecc_enable);
57 if (error)
58 dev_err(dev, "Failed to create sysfs attributes!\n");
59}
60
61void gp10b_remove_sysfs(struct device *dev)
62{
63 device_remove_file(dev, &dev_attr_ecc_enable);
64}
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h
new file mode 100644
index 00000000..786a3bb0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h
@@ -0,0 +1,29 @@
1/*
2 * GP10B specific sysfs files
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _GP10B_SYSFS_H_
17#define _GP10B_SYSFS_H_
18
19#include <linux/version.h>
20
21/*ECC Fuse*/
22#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
23#define FUSE_OPT_ECC_EN 0x358
24#endif
25
26void gp10b_create_sysfs(struct device *dev);
27void gp10b_remove_sysfs(struct device *dev);
28
29#endif /*_GP10B_SYSFS_H_*/
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c
new file mode 100644
index 00000000..2bb4a313
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c
@@ -0,0 +1,73 @@
1/*
2 * drivers/video/tegra/host/gp10b/gr_ctx_gp10b.c
3 *
4 * GM20B Graphics Context
5 *
6 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include "gk20a/gk20a.h"
23#include "gr_ctx_gp10b.h"
24
25static int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name)
26{
27 switch (index) {
28#ifdef GP10B_NETLIST_IMAGE_FW_NAME
29 case NETLIST_FINAL:
30 sprintf(name, GP10B_NETLIST_IMAGE_FW_NAME);
31 return 0;
32#endif
33#ifdef GK20A_NETLIST_IMAGE_A
34 case NETLIST_SLOT_A:
35 sprintf(name, GK20A_NETLIST_IMAGE_A);
36 return 0;
37#endif
38#ifdef GK20A_NETLIST_IMAGE_B
39 case NETLIST_SLOT_B:
40 sprintf(name, GK20A_NETLIST_IMAGE_B);
41 return 0;
42#endif
43#ifdef GK20A_NETLIST_IMAGE_C
44 case NETLIST_SLOT_C:
45 sprintf(name, GK20A_NETLIST_IMAGE_C);
46 return 0;
47#endif
48#ifdef GK20A_NETLIST_IMAGE_D
49 case NETLIST_SLOT_D:
50 sprintf(name, GK20A_NETLIST_IMAGE_D);
51 return 0;
52#endif
53 default:
54 return -1;
55 }
56
57 return -1;
58}
59
60static bool gr_gp10b_is_firmware_defined(void)
61{
62#ifdef GP10B_NETLIST_IMAGE_FW_NAME
63 return true;
64#else
65 return false;
66#endif
67}
68
69void gp10b_init_gr_ctx(struct gpu_ops *gops) {
70 gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name;
71 gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined;
72 gops->gr_ctx.use_dma_for_fw_bootstrap = true;
73}
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
new file mode 100644
index 00000000..b5c76d24
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
@@ -0,0 +1,28 @@
1/*
2 * GP10B Graphics Context
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __GR_CTX_GM10B_H__
19#define __GR_CTX_GM10B_H__
20
21#include "gk20a/gr_ctx_gk20a.h"
22
23/* production netlist, one and only one from below */
24#define GP10B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A
25
26void gp10b_init_gr_ctx(struct gpu_ops *gops);
27
28#endif /*__GR_CTX_GP10B_H__*/
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
new file mode 100644
index 00000000..9de7d675
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -0,0 +1,2257 @@
1/*
2 * GP10B GPU GR
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/tegra-fuse.h>
20#include <linux/version.h>
21
22#include <dt-bindings/soc/gm20b-fuse.h>
23#include <dt-bindings/soc/gp10b-fuse.h>
24
25#include "gk20a/gr_gk20a.h"
26#include "gk20a/semaphore_gk20a.h"
27#include "gk20a/dbg_gpu_gk20a.h"
28
29#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */
30#include "gp10b/gr_gp10b.h"
31#include "hw_gr_gp10b.h"
32#include "hw_fifo_gp10b.h"
33#include "hw_ctxsw_prog_gp10b.h"
34#include "hw_mc_gp10b.h"
35#include "gp10b_sysfs.h"
36#include <linux/vmalloc.h>
37
38#define NVGPU_GFXP_WFI_TIMEOUT_US 100LL
39
40static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num)
41{
42 bool valid = false;
43
44 switch (class_num) {
45 case PASCAL_COMPUTE_A:
46 case PASCAL_A:
47 case PASCAL_DMA_COPY_A:
48 valid = true;
49 break;
50
51 case MAXWELL_COMPUTE_B:
52 case MAXWELL_B:
53 case FERMI_TWOD_A:
54 case KEPLER_DMA_COPY_A:
55 case MAXWELL_DMA_COPY_A:
56 valid = true;
57 break;
58
59 default:
60 break;
61 }
62 gk20a_dbg_info("class=0x%x valid=%d", class_num, valid);
63 return valid;
64}
65
66static void gr_gp10b_sm_lrf_ecc_overcount_war(int single_err,
67 u32 sed_status,
68 u32 ded_status,
69 u32 *count_to_adjust,
70 u32 opposite_count)
71{
72 u32 over_count = 0;
73
74 sed_status >>= gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_b();
75 ded_status >>= gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_b();
76
77 /* One overcount for each partition on which a SBE occurred but not a
78 DBE (or vice-versa) */
79 if (single_err) {
80 over_count =
81 hweight32(sed_status & ~ded_status);
82 } else {
83 over_count =
84 hweight32(ded_status & ~sed_status);
85 }
86
87 /* If both a SBE and a DBE occur on the same partition, then we have an
88 overcount for the subpartition if the opposite error counts are
89 zero. */
90 if ((sed_status & ded_status) && (opposite_count == 0)) {
91 over_count +=
92 hweight32(sed_status & ded_status);
93 }
94
95 if (*count_to_adjust > over_count)
96 *count_to_adjust -= over_count;
97 else
98 *count_to_adjust = 0;
99}
100
101static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
102 bool *post_event, struct channel_gk20a *fault_ch,
103 u32 *hww_global_esr)
104{
105 int ret = 0;
106 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
107 u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
108 u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
109 u32 lrf_ecc_status, lrf_ecc_sed_status, lrf_ecc_ded_status;
110 u32 lrf_single_count_delta, lrf_double_count_delta;
111 u32 shm_ecc_status;
112
113 gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
114
115 /* Check for LRF ECC errors. */
116 lrf_ecc_status = gk20a_readl(g,
117 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset);
118 lrf_ecc_sed_status = lrf_ecc_status &
119 (gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f() |
120 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f() |
121 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f() |
122 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f());
123 lrf_ecc_ded_status = lrf_ecc_status &
124 (gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f() |
125 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f() |
126 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f() |
127 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f());
128 lrf_single_count_delta =
129 gk20a_readl(g,
130 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() +
131 offset);
132 lrf_double_count_delta =
133 gk20a_readl(g,
134 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() +
135 offset);
136 gk20a_writel(g,
137 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset,
138 0);
139 gk20a_writel(g,
140 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset,
141 0);
142 if (lrf_ecc_sed_status) {
143 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
144 "Single bit error detected in SM LRF!");
145
146 gr_gp10b_sm_lrf_ecc_overcount_war(1,
147 lrf_ecc_sed_status,
148 lrf_ecc_ded_status,
149 &lrf_single_count_delta,
150 lrf_double_count_delta);
151 g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] +=
152 lrf_single_count_delta;
153 }
154 if (lrf_ecc_ded_status) {
155 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
156 "Double bit error detected in SM LRF!");
157
158 gr_gp10b_sm_lrf_ecc_overcount_war(0,
159 lrf_ecc_sed_status,
160 lrf_ecc_ded_status,
161 &lrf_double_count_delta,
162 lrf_single_count_delta);
163 g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] +=
164 lrf_double_count_delta;
165 }
166 gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
167 lrf_ecc_status);
168
169 /* Check for SHM ECC errors. */
170 shm_ecc_status = gk20a_readl(g,
171 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset);
172 if ((shm_ecc_status &
173 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) ||
174 (shm_ecc_status &
175 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()) ||
176 (shm_ecc_status &
177 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) ||
178 (shm_ecc_status &
179 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) {
180 u32 ecc_stats_reg_val;
181
182 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
183 "Single bit error detected in SM SHM!");
184
185 ecc_stats_reg_val =
186 gk20a_readl(g,
187 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
188 g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] +=
189 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val);
190 g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] +=
191 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val);
192 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() |
193 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m());
194 gk20a_writel(g,
195 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
196 ecc_stats_reg_val);
197 }
198 if ( (shm_ecc_status &
199 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) ||
200 (shm_ecc_status &
201 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) {
202 u32 ecc_stats_reg_val;
203
204 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
205 "Double bit error detected in SM SHM!");
206
207 ecc_stats_reg_val =
208 gk20a_readl(g,
209 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
210 g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] +=
211 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val);
212 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m());
213 gk20a_writel(g,
214 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
215 ecc_stats_reg_val);
216 }
217 gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset,
218 shm_ecc_status);
219
220
221 return ret;
222}
223
224static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
225 bool *post_event)
226{
227 int ret = 0;
228 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
229 u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
230 u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
231 u32 esr;
232 u32 ecc_stats_reg_val;
233
234 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "");
235
236 esr = gk20a_readl(g,
237 gr_gpc0_tpc0_tex_m_hww_esr_r() + offset);
238 gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr);
239
240 if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) {
241 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
242 "Single bit error detected in TEX!");
243
244 /* Pipe 0 counters */
245 gk20a_writel(g,
246 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
247 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
248
249 ecc_stats_reg_val = gk20a_readl(g,
250 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
251 g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] +=
252 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
253 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
254 gk20a_writel(g,
255 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
256 ecc_stats_reg_val);
257
258 ecc_stats_reg_val = gk20a_readl(g,
259 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
260 g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] +=
261 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
262 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
263 gk20a_writel(g,
264 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
265 ecc_stats_reg_val);
266
267
268 /* Pipe 1 counters */
269 gk20a_writel(g,
270 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
271 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
272
273 ecc_stats_reg_val = gk20a_readl(g,
274 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
275 g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] +=
276 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
277 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
278 gk20a_writel(g,
279 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
280 ecc_stats_reg_val);
281
282 ecc_stats_reg_val = gk20a_readl(g,
283 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
284 g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] +=
285 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
286 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
287 gk20a_writel(g,
288 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
289 ecc_stats_reg_val);
290
291
292 gk20a_writel(g,
293 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
294 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
295 }
296 if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) {
297 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
298 "Double bit error detected in TEX!");
299
300 /* Pipe 0 counters */
301 gk20a_writel(g,
302 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
303 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
304
305 ecc_stats_reg_val = gk20a_readl(g,
306 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
307 g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] +=
308 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
309 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
310 gk20a_writel(g,
311 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
312 ecc_stats_reg_val);
313
314 ecc_stats_reg_val = gk20a_readl(g,
315 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
316 g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] +=
317 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
318 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
319 gk20a_writel(g,
320 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
321 ecc_stats_reg_val);
322
323
324 /* Pipe 1 counters */
325 gk20a_writel(g,
326 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
327 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
328
329 ecc_stats_reg_val = gk20a_readl(g,
330 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
331 g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] +=
332 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
333 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
334 gk20a_writel(g,
335 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
336 ecc_stats_reg_val);
337
338 ecc_stats_reg_val = gk20a_readl(g,
339 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
340 g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] +=
341 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
342 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
343 gk20a_writel(g,
344 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
345 ecc_stats_reg_val);
346
347
348 gk20a_writel(g,
349 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
350 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
351 }
352
353 gk20a_writel(g,
354 gr_gpc0_tpc0_tex_m_hww_esr_r() + offset,
355 esr | gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f());
356
357 return ret;
358}
359
360static int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
361 struct channel_gk20a *c, bool patch)
362{
363 struct gr_gk20a *gr = &g->gr;
364 struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
365 struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
366 u32 attrib_offset_in_chunk = 0;
367 u32 alpha_offset_in_chunk = 0;
368 u32 pd_ab_max_output;
369 u32 gpc_index, ppc_index;
370 u32 temp, temp2;
371 u32 cbm_cfg_size_beta, cbm_cfg_size_alpha, cbm_cfg_size_steadystate;
372 u32 attrib_size_in_chunk, cb_attrib_cache_size_init;
373 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
374 u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
375 u32 num_pes_per_gpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_PES_PER_GPC);
376
377 gk20a_dbg_fn("");
378
379 if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) {
380 attrib_size_in_chunk = gr->attrib_cb_default_size +
381 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
382 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
383 cb_attrib_cache_size_init = gr->attrib_cb_default_size +
384 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
385 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
386 } else {
387 attrib_size_in_chunk = gr->attrib_cb_size;
388 cb_attrib_cache_size_init = gr->attrib_cb_default_size;
389 }
390
391 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(),
392 gr->attrib_cb_default_size, patch);
393 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_alpha_r(),
394 gr->alpha_cb_default_size, patch);
395
396 pd_ab_max_output = (gr->alpha_cb_default_size *
397 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) /
398 gr_pd_ab_dist_cfg1_max_output_granularity_v();
399
400 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(),
401 gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) |
402 gr_pd_ab_dist_cfg1_max_batches_init_f(), patch);
403
404 attrib_offset_in_chunk = alpha_offset_in_chunk +
405 gr->tpc_count * gr->alpha_cb_size;
406
407 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
408 temp = gpc_stride * gpc_index;
409 temp2 = num_pes_per_gpc * gpc_index;
410 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
411 ppc_index++) {
412 cbm_cfg_size_beta = cb_attrib_cache_size_init *
413 gr->pes_tpc_count[ppc_index][gpc_index];
414 cbm_cfg_size_alpha = gr->alpha_cb_default_size *
415 gr->pes_tpc_count[ppc_index][gpc_index];
416 cbm_cfg_size_steadystate = gr->attrib_cb_default_size *
417 gr->pes_tpc_count[ppc_index][gpc_index];
418
419 gr_gk20a_ctx_patch_write(g, ch_ctx,
420 gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp +
421 ppc_in_gpc_stride * ppc_index,
422 cbm_cfg_size_beta, patch);
423
424 gr_gk20a_ctx_patch_write(g, ch_ctx,
425 gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp +
426 ppc_in_gpc_stride * ppc_index,
427 attrib_offset_in_chunk, patch);
428
429 gr_gk20a_ctx_patch_write(g, ch_ctx,
430 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp +
431 ppc_in_gpc_stride * ppc_index,
432 cbm_cfg_size_steadystate,
433 patch);
434
435 attrib_offset_in_chunk += attrib_size_in_chunk *
436 gr->pes_tpc_count[ppc_index][gpc_index];
437
438 gr_gk20a_ctx_patch_write(g, ch_ctx,
439 gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp +
440 ppc_in_gpc_stride * ppc_index,
441 cbm_cfg_size_alpha, patch);
442
443 gr_gk20a_ctx_patch_write(g, ch_ctx,
444 gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp +
445 ppc_in_gpc_stride * ppc_index,
446 alpha_offset_in_chunk, patch);
447
448 alpha_offset_in_chunk += gr->alpha_cb_size *
449 gr->pes_tpc_count[ppc_index][gpc_index];
450
451 gr_gk20a_ctx_patch_write(g, ch_ctx,
452 gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + temp2),
453 gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size_steadystate),
454 patch);
455 }
456 }
457
458 return 0;
459}
460
461static void gr_gp10b_commit_global_pagepool(struct gk20a *g,
462 struct channel_ctx_gk20a *ch_ctx,
463 u64 addr, u32 size, bool patch)
464{
465 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_base_r(),
466 gr_scc_pagepool_base_addr_39_8_f(addr), patch);
467
468 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_r(),
469 gr_scc_pagepool_total_pages_f(size) |
470 gr_scc_pagepool_valid_true_f(), patch);
471
472 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_base_r(),
473 gr_gpcs_gcc_pagepool_base_addr_39_8_f(addr), patch);
474
475 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_r(),
476 gr_gpcs_gcc_pagepool_total_pages_f(size), patch);
477}
478
479static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
480 struct zbc_entry *color_val, u32 index)
481{
482 u32 i;
483 u32 zbc_c;
484
485 /* update l2 table */
486 g->ops.ltc.set_zbc_color_entry(g, color_val, index);
487
488 /* update ds table */
489 gk20a_writel(g, gr_ds_zbc_color_r_r(),
490 gr_ds_zbc_color_r_val_f(color_val->color_ds[0]));
491 gk20a_writel(g, gr_ds_zbc_color_g_r(),
492 gr_ds_zbc_color_g_val_f(color_val->color_ds[1]));
493 gk20a_writel(g, gr_ds_zbc_color_b_r(),
494 gr_ds_zbc_color_b_val_f(color_val->color_ds[2]));
495 gk20a_writel(g, gr_ds_zbc_color_a_r(),
496 gr_ds_zbc_color_a_val_f(color_val->color_ds[3]));
497
498 gk20a_writel(g, gr_ds_zbc_color_fmt_r(),
499 gr_ds_zbc_color_fmt_val_f(color_val->format));
500
501 gk20a_writel(g, gr_ds_zbc_tbl_index_r(),
502 gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE));
503
504 /* trigger the write */
505 gk20a_writel(g, gr_ds_zbc_tbl_ld_r(),
506 gr_ds_zbc_tbl_ld_select_c_f() |
507 gr_ds_zbc_tbl_ld_action_write_f() |
508 gr_ds_zbc_tbl_ld_trigger_active_f());
509
510 /* update local copy */
511 for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) {
512 gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i];
513 gr->zbc_col_tbl[index].color_ds[i] = color_val->color_ds[i];
514 }
515 gr->zbc_col_tbl[index].format = color_val->format;
516 gr->zbc_col_tbl[index].ref_cnt++;
517
518 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index),
519 color_val->color_ds[0]);
520 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index),
521 color_val->color_ds[1]);
522 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index),
523 color_val->color_ds[2]);
524 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index),
525 color_val->color_ds[3]);
526 zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3));
527 zbc_c &= ~(0x7f << ((index % 4) * 7));
528 zbc_c |= color_val->format << ((index % 4) * 7);
529 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c);
530
531 return 0;
532}
533
534static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
535 struct zbc_entry *depth_val, u32 index)
536{
537 u32 zbc_z;
538
539 /* update l2 table */
540 g->ops.ltc.set_zbc_depth_entry(g, depth_val, index);
541
542 /* update ds table */
543 gk20a_writel(g, gr_ds_zbc_z_r(),
544 gr_ds_zbc_z_val_f(depth_val->depth));
545
546 gk20a_writel(g, gr_ds_zbc_z_fmt_r(),
547 gr_ds_zbc_z_fmt_val_f(depth_val->format));
548
549 gk20a_writel(g, gr_ds_zbc_tbl_index_r(),
550 gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE));
551
552 /* trigger the write */
553 gk20a_writel(g, gr_ds_zbc_tbl_ld_r(),
554 gr_ds_zbc_tbl_ld_select_z_f() |
555 gr_ds_zbc_tbl_ld_action_write_f() |
556 gr_ds_zbc_tbl_ld_trigger_active_f());
557
558 /* update local copy */
559 gr->zbc_dep_tbl[index].depth = depth_val->depth;
560 gr->zbc_dep_tbl[index].format = depth_val->format;
561 gr->zbc_dep_tbl[index].ref_cnt++;
562
563 gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth);
564 zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3));
565 zbc_z &= ~(0x7f << (index % 4) * 7);
566 zbc_z |= depth_val->format << (index % 4) * 7;
567 gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z);
568
569 return 0;
570}
571
572static u32 gr_gp10b_pagepool_default_size(struct gk20a *g)
573{
574 return gr_scc_pagepool_total_pages_hwmax_value_v();
575}
576
577static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g)
578{
579 struct gr_gk20a *gr = &g->gr;
580 int size;
581
582 gr->attrib_cb_size = gr->attrib_cb_default_size;
583 gr->alpha_cb_size = gr->alpha_cb_default_size;
584
585 gr->attrib_cb_size = min(gr->attrib_cb_size,
586 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(~0) / g->gr.tpc_count);
587 gr->alpha_cb_size = min(gr->alpha_cb_size,
588 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(~0) / g->gr.tpc_count);
589
590 size = gr->attrib_cb_size *
591 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
592 gr->max_tpc_count;
593
594 size += gr->alpha_cb_size *
595 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() *
596 gr->max_tpc_count;
597
598 size = ALIGN(size, 128);
599
600 return size;
601}
602
603static void gr_gp10b_set_go_idle_timeout(struct gk20a *g, u32 data)
604{
605 gk20a_writel(g, gr_fe_go_idle_timeout_r(), data);
606}
607
608static void gr_gp10b_set_coalesce_buffer_size(struct gk20a *g, u32 data)
609{
610 u32 val;
611
612 gk20a_dbg_fn("");
613
614 val = gk20a_readl(g, gr_gpcs_tc_debug0_r());
615 val = set_field(val, gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(),
616 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(data));
617 gk20a_writel(g, gr_gpcs_tc_debug0_r(), val);
618
619 gk20a_dbg_fn("done");
620}
621
622static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
623 u32 class_num, u32 offset, u32 data)
624{
625 gk20a_dbg_fn("");
626
627 if (class_num == PASCAL_COMPUTE_A) {
628 switch (offset << 2) {
629 case NVC0C0_SET_SHADER_EXCEPTIONS:
630 gk20a_gr_set_shader_exceptions(g, data);
631 break;
632 default:
633 goto fail;
634 }
635 }
636
637 if (class_num == PASCAL_A) {
638 switch (offset << 2) {
639 case NVC097_SET_SHADER_EXCEPTIONS:
640 gk20a_gr_set_shader_exceptions(g, data);
641 break;
642 case NVC097_SET_CIRCULAR_BUFFER_SIZE:
643 g->ops.gr.set_circular_buffer_size(g, data);
644 break;
645 case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
646 g->ops.gr.set_alpha_circular_buffer_size(g, data);
647 break;
648 case NVC097_SET_GO_IDLE_TIMEOUT:
649 gr_gp10b_set_go_idle_timeout(g, data);
650 break;
651 case NVC097_SET_COALESCE_BUFFER_SIZE:
652 gr_gp10b_set_coalesce_buffer_size(g, data);
653 break;
654 default:
655 goto fail;
656 }
657 }
658 return 0;
659
660fail:
661 return -EINVAL;
662}
663
664static void gr_gp10b_cb_size_default(struct gk20a *g)
665{
666 struct gr_gk20a *gr = &g->gr;
667
668 if (!gr->attrib_cb_default_size)
669 gr->attrib_cb_default_size = 0x800;
670 gr->alpha_cb_default_size =
671 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
672}
673
674static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
675{
676 struct gr_gk20a *gr = &g->gr;
677 u32 gpc_index, ppc_index, stride, val;
678 u32 pd_ab_max_output;
679 u32 alpha_cb_size = data * 4;
680 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
681 u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
682
683 gk20a_dbg_fn("");
684
685 if (alpha_cb_size > gr->alpha_cb_size)
686 alpha_cb_size = gr->alpha_cb_size;
687
688 gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(),
689 (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) &
690 ~gr_ds_tga_constraintlogic_alpha_cbsize_f(~0)) |
691 gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size));
692
693 pd_ab_max_output = alpha_cb_size *
694 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() /
695 gr_pd_ab_dist_cfg1_max_output_granularity_v();
696
697 gk20a_writel(g, gr_pd_ab_dist_cfg1_r(),
698 gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) |
699 gr_pd_ab_dist_cfg1_max_batches_init_f());
700
701 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
702 stride = gpc_stride * gpc_index;
703
704 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
705 ppc_index++) {
706
707 val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() +
708 stride +
709 ppc_in_gpc_stride * ppc_index);
710
711 val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(),
712 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size *
713 gr->pes_tpc_count[ppc_index][gpc_index]));
714
715 gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() +
716 stride +
717 ppc_in_gpc_stride * ppc_index, val);
718 }
719 }
720}
721
722static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
723{
724 struct gr_gk20a *gr = &g->gr;
725 u32 gpc_index, ppc_index, stride, val;
726 u32 cb_size_steady = data * 4, cb_size;
727 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
728 u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
729
730 gk20a_dbg_fn("");
731
732 if (cb_size_steady > gr->attrib_cb_size)
733 cb_size_steady = gr->attrib_cb_size;
734 if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) !=
735 gk20a_readl(g,
736 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) {
737 cb_size = cb_size_steady +
738 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
739 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
740 } else {
741 cb_size = cb_size_steady;
742 }
743
744 gk20a_writel(g, gr_ds_tga_constraintlogic_beta_r(),
745 (gk20a_readl(g, gr_ds_tga_constraintlogic_beta_r()) &
746 ~gr_ds_tga_constraintlogic_beta_cbsize_f(~0)) |
747 gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size_steady));
748
749 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
750 stride = gpc_stride * gpc_index;
751
752 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
753 ppc_index++) {
754
755 val = gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
756 stride +
757 ppc_in_gpc_stride * ppc_index);
758
759 val = set_field(val,
760 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(),
761 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(cb_size *
762 gr->pes_tpc_count[ppc_index][gpc_index]));
763
764 gk20a_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
765 stride +
766 ppc_in_gpc_stride * ppc_index, val);
767
768 gk20a_writel(g, ppc_in_gpc_stride * ppc_index +
769 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() +
770 stride,
771 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(
772 cb_size_steady));
773
774 val = gk20a_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r(
775 ppc_index + gpc_index));
776
777 val = set_field(val,
778 gr_gpcs_swdx_tc_beta_cb_size_v_m(),
779 gr_gpcs_swdx_tc_beta_cb_size_v_f(
780 cb_size_steady *
781 gr->gpc_ppc_count[gpc_index]));
782
783 gk20a_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r(
784 ppc_index + gpc_index), val);
785 }
786 }
787}
788
789static int gr_gp10b_init_ctx_state(struct gk20a *g)
790{
791 struct fecs_method_op_gk20a op = {
792 .mailbox = { .id = 0, .data = 0,
793 .clr = ~0, .ok = 0, .fail = 0},
794 .method.data = 0,
795 .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL,
796 .cond.fail = GR_IS_UCODE_OP_SKIP,
797 };
798 int err;
799
800 gk20a_dbg_fn("");
801
802 err = gr_gk20a_init_ctx_state(g);
803 if (err)
804 return err;
805
806 if (!g->gr.t18x.ctx_vars.preempt_image_size) {
807 op.method.addr =
808 gr_fecs_method_push_adr_discover_preemption_image_size_v();
809 op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size;
810 err = gr_gk20a_submit_fecs_method_op(g, op, false);
811 if (err) {
812 gk20a_err(dev_from_gk20a(g),
813 "query preempt image size failed");
814 return err;
815 }
816 }
817
818 gk20a_dbg_info("preempt image size: %u",
819 g->gr.t18x.ctx_vars.preempt_image_size);
820
821 gk20a_dbg_fn("done");
822
823 return 0;
824}
825
826int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
827 struct mem_desc *mem)
828{
829 int err;
830
831 gk20a_dbg_fn("");
832
833 err = gk20a_gmmu_alloc_sys(vm->mm->g, size, mem);
834 if (err)
835 return err;
836
837 mem->gpu_va = gk20a_gmmu_map(vm,
838 &mem->sgt,
839 size,
840 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
841 gk20a_mem_flag_none,
842 false,
843 mem->aperture);
844
845 if (!mem->gpu_va) {
846 err = -ENOMEM;
847 goto fail_free;
848 }
849
850 return 0;
851
852fail_free:
853 gk20a_gmmu_free(vm->mm->g, mem);
854 return err;
855}
856
857static int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
858 struct gr_ctx_desc *gr_ctx,
859 struct vm_gk20a *vm, u32 class,
860 u32 graphics_preempt_mode,
861 u32 compute_preempt_mode)
862{
863 int err = 0;
864
865 if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp)
866 graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
867
868 if (class == PASCAL_COMPUTE_A &&
869 g->gr.t18x.ctx_vars.force_preemption_cilp)
870 compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
871
872 /* check for invalid combinations */
873 if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0))
874 return -EINVAL;
875
876 if ((graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) &&
877 (compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP))
878 return -EINVAL;
879
880 /* Do not allow lower preemption modes than current ones */
881 if (graphics_preempt_mode &&
882 (graphics_preempt_mode < gr_ctx->graphics_preempt_mode))
883 return -EINVAL;
884
885 if (compute_preempt_mode &&
886 (compute_preempt_mode < gr_ctx->compute_preempt_mode))
887 return -EINVAL;
888
889 /* set preemption modes */
890 switch (graphics_preempt_mode) {
891 case NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP:
892 {
893 u32 spill_size =
894 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
895 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
896 u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
897 gr_scc_pagepool_total_pages_byte_granularity_v();
898 u32 betacb_size = g->gr.attrib_cb_default_size +
899 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
900 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
901 u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
902 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
903 g->gr.max_tpc_count;
904 attrib_cb_size = ALIGN(attrib_cb_size, 128);
905
906 gk20a_dbg_info("gfxp context spill_size=%d", spill_size);
907 gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size);
908 gk20a_dbg_info("gfxp context attrib_cb_size=%d",
909 attrib_cb_size);
910
911 err = gr_gp10b_alloc_buffer(vm,
912 g->gr.t18x.ctx_vars.preempt_image_size,
913 &gr_ctx->t18x.preempt_ctxsw_buffer);
914 if (err) {
915 gk20a_err(dev_from_gk20a(g),
916 "cannot allocate preempt buffer");
917 goto fail;
918 }
919
920 err = gr_gp10b_alloc_buffer(vm,
921 spill_size,
922 &gr_ctx->t18x.spill_ctxsw_buffer);
923 if (err) {
924 gk20a_err(dev_from_gk20a(g),
925 "cannot allocate spill buffer");
926 goto fail_free_preempt;
927 }
928
929 err = gr_gp10b_alloc_buffer(vm,
930 attrib_cb_size,
931 &gr_ctx->t18x.betacb_ctxsw_buffer);
932 if (err) {
933 gk20a_err(dev_from_gk20a(g),
934 "cannot allocate beta buffer");
935 goto fail_free_spill;
936 }
937
938 err = gr_gp10b_alloc_buffer(vm,
939 pagepool_size,
940 &gr_ctx->t18x.pagepool_ctxsw_buffer);
941 if (err) {
942 gk20a_err(dev_from_gk20a(g),
943 "cannot allocate page pool");
944 goto fail_free_betacb;
945 }
946
947 gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
948 break;
949 }
950
951 case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI:
952 gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
953 break;
954
955 default:
956 break;
957 }
958
959 if (class == PASCAL_COMPUTE_A) {
960 switch (compute_preempt_mode) {
961 case NVGPU_COMPUTE_PREEMPTION_MODE_WFI:
962 case NVGPU_COMPUTE_PREEMPTION_MODE_CTA:
963 case NVGPU_COMPUTE_PREEMPTION_MODE_CILP:
964 gr_ctx->compute_preempt_mode = compute_preempt_mode;
965 break;
966 default:
967 break;
968 }
969 }
970
971 return 0;
972
973fail_free_betacb:
974 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
975fail_free_spill:
976 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
977fail_free_preempt:
978 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
979fail:
980 return err;
981}
982
983static int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
984 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
985 u32 class,
986 u32 flags)
987{
988 int err;
989 u32 graphics_preempt_mode = 0;
990 u32 compute_preempt_mode = 0;
991
992 gk20a_dbg_fn("");
993
994 err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags);
995 if (err)
996 return err;
997
998 (*gr_ctx)->t18x.ctx_id_valid = false;
999
1000 if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP)
1001 graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
1002 if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP)
1003 compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
1004
1005 if (graphics_preempt_mode || compute_preempt_mode) {
1006 if (g->ops.gr.set_ctxsw_preemption_mode) {
1007 err = g->ops.gr.set_ctxsw_preemption_mode(g, *gr_ctx, vm,
1008 class, graphics_preempt_mode, compute_preempt_mode);
1009 if (err) {
1010 gk20a_err(dev_from_gk20a(g),
1011 "set_ctxsw_preemption_mode failed");
1012 goto fail_free_gk20a_ctx;
1013 }
1014 } else
1015 goto fail_free_gk20a_ctx;
1016 }
1017
1018 gk20a_dbg_fn("done");
1019
1020 return 0;
1021
1022fail_free_gk20a_ctx:
1023 gr_gk20a_free_gr_ctx(g, vm, *gr_ctx);
1024 *gr_ctx = NULL;
1025
1026 return err;
1027}
1028
1029static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm,
1030 struct gr_ctx_desc *gr_ctx)
1031{
1032 struct mem_desc *mem = &gr_ctx->mem;
1033
1034 if (gk20a_mem_begin(g, mem)) {
1035 WARN_ON("Cannot map context");
1036 return;
1037 }
1038 gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n",
1039 gk20a_mem_rd(g, mem,
1040 ctxsw_prog_main_image_magic_value_o()),
1041 ctxsw_prog_main_image_magic_value_v_value_v());
1042
1043 gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n",
1044 gk20a_mem_rd(g, mem,
1045 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o()));
1046
1047 gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n",
1048 gk20a_mem_rd(g, mem,
1049 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o()));
1050
1051 gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n",
1052 gk20a_mem_rd(g, mem,
1053 ctxsw_prog_main_image_context_timestamp_buffer_control_o()));
1054
1055 gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n",
1056 gk20a_mem_rd(g, mem,
1057 ctxsw_prog_main_image_num_save_ops_o()));
1058 gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n",
1059 gk20a_mem_rd(g, mem,
1060 ctxsw_prog_main_image_num_wfi_save_ops_o()));
1061 gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n",
1062 gk20a_mem_rd(g, mem,
1063 ctxsw_prog_main_image_num_cta_save_ops_o()));
1064 gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n",
1065 gk20a_mem_rd(g, mem,
1066 ctxsw_prog_main_image_num_gfxp_save_ops_o()));
1067 gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n",
1068 gk20a_mem_rd(g, mem,
1069 ctxsw_prog_main_image_num_cilp_save_ops_o()));
1070 gk20a_err(dev_from_gk20a(g),
1071 "image gfx preemption option (GFXP is 1) %x\n",
1072 gk20a_mem_rd(g, mem,
1073 ctxsw_prog_main_image_graphics_preemption_options_o()));
1074 gk20a_mem_end(g, mem);
1075}
1076
1077static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
1078 struct gr_ctx_desc *gr_ctx)
1079{
1080 gk20a_dbg_fn("");
1081
1082 if (!gr_ctx)
1083 return;
1084
1085 if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close)
1086 dump_ctx_switch_stats(g, vm, gr_ctx);
1087
1088 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer);
1089 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
1090 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
1091 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
1092 gr_gk20a_free_gr_ctx(g, vm, gr_ctx);
1093 gk20a_dbg_fn("done");
1094}
1095
1096
1097static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
1098 struct channel_ctx_gk20a *ch_ctx,
1099 struct mem_desc *mem)
1100{
1101 struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
1102 u32 gfxp_preempt_option =
1103 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f();
1104 u32 cilp_preempt_option =
1105 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f();
1106 u32 cta_preempt_option =
1107 ctxsw_prog_main_image_compute_preemption_options_control_cta_f();
1108 int err;
1109
1110 gk20a_dbg_fn("");
1111
1112 if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) {
1113 gk20a_dbg_info("GfxP: %x", gfxp_preempt_option);
1114 gk20a_mem_wr(g, mem,
1115 ctxsw_prog_main_image_graphics_preemption_options_o(),
1116 gfxp_preempt_option);
1117 }
1118
1119 if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) {
1120 gk20a_dbg_info("CILP: %x", cilp_preempt_option);
1121 gk20a_mem_wr(g, mem,
1122 ctxsw_prog_main_image_compute_preemption_options_o(),
1123 cilp_preempt_option);
1124 }
1125
1126 if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CTA) {
1127 gk20a_dbg_info("CTA: %x", cta_preempt_option);
1128 gk20a_mem_wr(g, mem,
1129 ctxsw_prog_main_image_compute_preemption_options_o(),
1130 cta_preempt_option);
1131 }
1132
1133 if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) {
1134 u32 addr;
1135 u32 size;
1136 u32 cbes_reserve;
1137
1138 gk20a_mem_wr(g, mem,
1139 ctxsw_prog_main_image_full_preemption_ptr_o(),
1140 gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8);
1141
1142 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx);
1143 if (err) {
1144 gk20a_err(dev_from_gk20a(g),
1145 "can't map patch context");
1146 goto out;
1147 }
1148
1149 addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >>
1150 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) |
1151 (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) <<
1152 (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()));
1153
1154 gk20a_dbg_info("attrib cb addr : 0x%016x", addr);
1155 g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true);
1156
1157 addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >>
1158 gr_scc_pagepool_base_addr_39_8_align_bits_v()) |
1159 (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) <<
1160 (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v()));
1161 size = gr_ctx->t18x.pagepool_ctxsw_buffer.size;
1162
1163 if (size == g->ops.gr.pagepool_default_size(g))
1164 size = gr_scc_pagepool_total_pages_hwmax_v();
1165
1166 g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true);
1167
1168 addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >>
1169 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) |
1170 (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) <<
1171 (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()));
1172 size = gr_ctx->t18x.spill_ctxsw_buffer.size /
1173 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
1174
1175 gr_gk20a_ctx_patch_write(g, ch_ctx,
1176 gr_gpc0_swdx_rm_spill_buffer_addr_r(),
1177 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(addr),
1178 true);
1179 gr_gk20a_ctx_patch_write(g, ch_ctx,
1180 gr_gpc0_swdx_rm_spill_buffer_size_r(),
1181 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size),
1182 true);
1183
1184 cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v();
1185 gr_gk20a_ctx_patch_write(g, ch_ctx,
1186 gr_gpcs_swdx_beta_cb_ctrl_r(),
1187 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(
1188 cbes_reserve),
1189 true);
1190 gr_gk20a_ctx_patch_write(g, ch_ctx,
1191 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(),
1192 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(
1193 cbes_reserve),
1194 true);
1195
1196 gr_gk20a_ctx_patch_write_end(g, ch_ctx);
1197 }
1198
1199out:
1200 gk20a_dbg_fn("done");
1201}
1202
1203static int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
1204 struct gk20a_debug_output *o)
1205{
1206 struct gr_gk20a *gr = &g->gr;
1207 u32 gr_engine_id;
1208
1209 gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
1210
1211 gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
1212 gk20a_readl(g, gr_status_r()));
1213 gk20a_debug_output(o, "NV_PGRAPH_STATUS1: 0x%x\n",
1214 gk20a_readl(g, gr_status_1_r()));
1215 gk20a_debug_output(o, "NV_PGRAPH_STATUS2: 0x%x\n",
1216 gk20a_readl(g, gr_status_2_r()));
1217 gk20a_debug_output(o, "NV_PGRAPH_ENGINE_STATUS: 0x%x\n",
1218 gk20a_readl(g, gr_engine_status_r()));
1219 gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_STATUS : 0x%x\n",
1220 gk20a_readl(g, gr_gpfifo_status_r()));
1221 gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_CONTROL : 0x%x\n",
1222 gk20a_readl(g, gr_gpfifo_ctl_r()));
1223 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n",
1224 gk20a_readl(g, gr_fecs_host_int_status_r()));
1225 gk20a_debug_output(o, "NV_PGRAPH_EXCEPTION : 0x%x\n",
1226 gk20a_readl(g, gr_exception_r()));
1227 gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n",
1228 gk20a_readl(g, gr_fecs_intr_r()));
1229 gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
1230 gk20a_readl(g, fifo_engine_status_r(gr_engine_id)));
1231 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
1232 gk20a_readl(g, gr_activity_0_r()));
1233 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",
1234 gk20a_readl(g, gr_activity_1_r()));
1235 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY2: 0x%x\n",
1236 gk20a_readl(g, gr_activity_2_r()));
1237 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY4: 0x%x\n",
1238 gk20a_readl(g, gr_activity_4_r()));
1239 gk20a_debug_output(o, "NV_PGRAPH_PRI_SKED_ACTIVITY: 0x%x\n",
1240 gk20a_readl(g, gr_pri_sked_activity_r()));
1241 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0: 0x%x\n",
1242 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity0_r()));
1243 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1: 0x%x\n",
1244 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity1_r()));
1245 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2: 0x%x\n",
1246 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity2_r()));
1247 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3: 0x%x\n",
1248 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r()));
1249 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1250 gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r()));
1251 if (gr->gpc_tpc_count[0] == 2)
1252 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1253 gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r()));
1254 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1255 gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r()));
1256 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n",
1257 gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_0_r()));
1258 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1: 0x%x\n",
1259 gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_1_r()));
1260 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2: 0x%x\n",
1261 gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_2_r()));
1262 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3: 0x%x\n",
1263 gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r()));
1264 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1265 gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r()));
1266 if (gr->gpc_tpc_count[0] == 2)
1267 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1268 gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r()));
1269 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1270 gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r()));
1271 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n",
1272 gk20a_readl(g, gr_pri_be0_becs_be_activity0_r()));
1273 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0: 0x%x\n",
1274 gk20a_readl(g, gr_pri_be1_becs_be_activity0_r()));
1275 gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0: 0x%x\n",
1276 gk20a_readl(g, gr_pri_bes_becs_be_activity0_r()));
1277 gk20a_debug_output(o, "NV_PGRAPH_PRI_DS_MPIPE_STATUS: 0x%x\n",
1278 gk20a_readl(g, gr_pri_ds_mpipe_status_r()));
1279 gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT : 0x%x\n",
1280 gk20a_readl(g, gr_fe_go_idle_timeout_r()));
1281 gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_INFO : 0x%x\n",
1282 gk20a_readl(g, gr_pri_fe_go_idle_info_r()));
1283 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS: 0x%x\n",
1284 gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r()));
1285 gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n",
1286 gk20a_readl(g, gr_cwd_fs_r()));
1287 gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n",
1288 gk20a_readl(g, gr_fe_tpc_fs_r()));
1289 gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n",
1290 gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0)));
1291 gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n",
1292 gk20a_readl(g, gr_cwd_sm_id_r(0)));
1293 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0: 0x%x\n",
1294 gk20a_readl(g, gr_fecs_ctxsw_status_fe_0_r()));
1295 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1: 0x%x\n",
1296 gk20a_readl(g, gr_fecs_ctxsw_status_1_r()));
1297 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0: 0x%x\n",
1298 gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_gpc_0_r()));
1299 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1: 0x%x\n",
1300 gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r()));
1301 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE : 0x%x\n",
1302 gk20a_readl(g, gr_fecs_ctxsw_idlestate_r()));
1303 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n",
1304 gk20a_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r()));
1305 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n",
1306 gk20a_readl(g, gr_fecs_current_ctx_r()));
1307 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n",
1308 gk20a_readl(g, gr_fecs_new_ctx_r()));
1309 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n",
1310 gk20a_readl(g, gr_pri_be0_crop_status1_r()));
1311 gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_CROP_STATUS1 : 0x%x\n",
1312 gk20a_readl(g, gr_pri_bes_crop_status1_r()));
1313 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS : 0x%x\n",
1314 gk20a_readl(g, gr_pri_be0_zrop_status_r()));
1315 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS2 : 0x%x\n",
1316 gk20a_readl(g, gr_pri_be0_zrop_status2_r()));
1317 gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS : 0x%x\n",
1318 gk20a_readl(g, gr_pri_bes_zrop_status_r()));
1319 gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS2 : 0x%x\n",
1320 gk20a_readl(g, gr_pri_bes_zrop_status2_r()));
1321 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION: 0x%x\n",
1322 gk20a_readl(g, gr_pri_be0_becs_be_exception_r()));
1323 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN: 0x%x\n",
1324 gk20a_readl(g, gr_pri_be0_becs_be_exception_en_r()));
1325 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n",
1326 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r()));
1327 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n",
1328 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r()));
1329 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n",
1330 gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r()));
1331 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n",
1332 gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r()));
1333 return 0;
1334}
1335
1336static bool gr_activity_empty_or_preempted(u32 val)
1337{
1338 while(val) {
1339 u32 v = val & 7;
1340 if (v != gr_activity_4_gpc0_empty_v() &&
1341 v != gr_activity_4_gpc0_preempted_v())
1342 return false;
1343 val >>= 3;
1344 }
1345
1346 return true;
1347}
1348
1349static int gr_gp10b_wait_empty(struct gk20a *g, unsigned long end_jiffies,
1350 u32 expect_delay)
1351{
1352 u32 delay = expect_delay;
1353 bool gr_enabled;
1354 bool ctxsw_active;
1355 bool gr_busy;
1356 u32 gr_status;
1357 u32 activity0, activity1, activity2, activity4;
1358
1359 gk20a_dbg_fn("");
1360
1361 do {
1362 /* fmodel: host gets fifo_engine_status(gr) from gr
1363 only when gr_status is read */
1364 gr_status = gk20a_readl(g, gr_status_r());
1365
1366 gr_enabled = gk20a_readl(g, mc_enable_r()) &
1367 mc_enable_pgraph_enabled_f();
1368
1369 ctxsw_active = gr_status & 1<<7;
1370
1371 activity0 = gk20a_readl(g, gr_activity_0_r());
1372 activity1 = gk20a_readl(g, gr_activity_1_r());
1373 activity2 = gk20a_readl(g, gr_activity_2_r());
1374 activity4 = gk20a_readl(g, gr_activity_4_r());
1375
1376 gr_busy = !(gr_activity_empty_or_preempted(activity0) &&
1377 gr_activity_empty_or_preempted(activity1) &&
1378 activity2 == 0 &&
1379 gr_activity_empty_or_preempted(activity4));
1380
1381 if (!gr_enabled || (!gr_busy && !ctxsw_active)) {
1382 gk20a_dbg_fn("done");
1383 return 0;
1384 }
1385
1386 usleep_range(delay, delay * 2);
1387 delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
1388
1389 } while (time_before(jiffies, end_jiffies)
1390 || !tegra_platform_is_silicon());
1391
1392 gk20a_err(dev_from_gk20a(g),
1393 "timeout, ctxsw busy : %d, gr busy : %d, %08x, %08x, %08x, %08x",
1394 ctxsw_active, gr_busy, activity0, activity1, activity2, activity4);
1395
1396 return -EAGAIN;
1397}
1398
1399static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
1400 struct channel_ctx_gk20a *ch_ctx,
1401 u64 addr, bool patch)
1402{
1403 struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
1404 int attrBufferSize;
1405
1406 if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va)
1407 attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size;
1408 else
1409 attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g);
1410
1411 attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f();
1412
1413 gr_gm20b_commit_global_attrib_cb(g, ch_ctx, addr, patch);
1414
1415 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(),
1416 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) |
1417 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch);
1418
1419 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_0_r(),
1420 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(addr), patch);
1421
1422 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_1_r(),
1423 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(attrBufferSize) |
1424 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch);
1425}
1426
1427static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
1428 struct channel_ctx_gk20a *ch_ctx,
1429 u64 addr, u64 size, bool patch)
1430{
1431 u32 data;
1432
1433 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_base_r(),
1434 gr_scc_bundle_cb_base_addr_39_8_f(addr), patch);
1435
1436 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_size_r(),
1437 gr_scc_bundle_cb_size_div_256b_f(size) |
1438 gr_scc_bundle_cb_size_valid_true_f(), patch);
1439
1440 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_base_r(),
1441 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(addr), patch);
1442
1443 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_size_r(),
1444 gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) |
1445 gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch);
1446
1447 /* data for state_limit */
1448 data = (g->gr.bundle_cb_default_size *
1449 gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) /
1450 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v();
1451
1452 data = min_t(u32, data, g->gr.min_gpm_fifo_depth);
1453
1454 gk20a_dbg_info("bundle cb token limit : %d, state limit : %d",
1455 g->gr.bundle_cb_token_limit, data);
1456
1457 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(),
1458 gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) |
1459 gr_pd_ab_dist_cfg2_state_limit_f(data), patch);
1460}
1461
1462static int gr_gp10b_load_smid_config(struct gk20a *g)
1463{
1464 u32 *tpc_sm_id;
1465 u32 i, j;
1466 u32 tpc_index, gpc_index;
1467 u32 max_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS);
1468
1469 tpc_sm_id = kcalloc(gr_cwd_sm_id__size_1_v(), sizeof(u32), GFP_KERNEL);
1470 if (!tpc_sm_id)
1471 return -ENOMEM;
1472
1473 /* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/
1474 for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) {
1475 u32 reg = 0;
1476 u32 bit_stride = gr_cwd_gpc_tpc_id_gpc0_s() +
1477 gr_cwd_gpc_tpc_id_tpc0_s();
1478
1479 for (j = 0; j < 4; j++) {
1480 u32 sm_id = (i * 4) + j;
1481 u32 bits;
1482
1483 if (sm_id >= g->gr.tpc_count)
1484 break;
1485
1486 gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index;
1487 tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index;
1488
1489 bits = gr_cwd_gpc_tpc_id_gpc0_f(gpc_index) |
1490 gr_cwd_gpc_tpc_id_tpc0_f(tpc_index);
1491 reg |= bits << (j * bit_stride);
1492
1493 tpc_sm_id[gpc_index + max_gpcs * ((tpc_index & 4) >> 2)]
1494 |= sm_id << (bit_stride * (tpc_index & 3));
1495 }
1496 gk20a_writel(g, gr_cwd_gpc_tpc_id_r(i), reg);
1497 }
1498
1499 for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++)
1500 gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]);
1501
1502 kfree(tpc_sm_id);
1503
1504 return 0;
1505}
1506
1507int gr_gp10b_init_fs_state(struct gk20a *g)
1508{
1509 u32 data;
1510
1511 gk20a_dbg_fn("");
1512
1513 data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r());
1514 data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(),
1515 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
1516 gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
1517
1518 data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r());
1519 data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(),
1520 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
1521 gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
1522
1523 if (g->gr.t18x.fecs_feature_override_ecc_val != 0) {
1524 gk20a_writel(g,
1525 gr_fecs_feature_override_ecc_r(),
1526 g->gr.t18x.fecs_feature_override_ecc_val);
1527 }
1528
1529 return gr_gm20b_init_fs_state(g);
1530}
1531
1532static void gr_gp10b_init_cyclestats(struct gk20a *g)
1533{
1534#if defined(CONFIG_GK20A_CYCLE_STATS)
1535 g->gpu_characteristics.flags |=
1536 NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS;
1537 g->gpu_characteristics.flags |=
1538 NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT;
1539#else
1540 (void)g;
1541#endif
1542}
1543
1544static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
1545{
1546 tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0);
1547 tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0);
1548
1549 if (g->gr.gpc_tpc_mask[gpc_index] == 0x1)
1550 tegra_fuse_control_write(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0);
1551 else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2)
1552 tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
1553 else
1554 tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
1555}
1556
1557static void gr_gp10b_get_access_map(struct gk20a *g,
1558 u32 **whitelist, int *num_entries)
1559{
1560 static u32 wl_addr_gp10b[] = {
1561 /* this list must be sorted (low to high) */
1562 0x404468, /* gr_pri_mme_max_instructions */
1563 0x418300, /* gr_pri_gpcs_rasterarb_line_class */
1564 0x418800, /* gr_pri_gpcs_setup_debug */
1565 0x418e00, /* gr_pri_gpcs_swdx_config */
1566 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1567 0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1568 0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1569 0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1570 0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1571 0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1572 0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1573 0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1574 0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1575 0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1576 0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1577 0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1578 0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1579 0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1580 0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1581 0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1582 0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1583 0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1584 0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1585 0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1586 0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1587 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */
1588 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */
1589 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */
1590 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */
1591 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */
1592 };
1593
1594 *whitelist = wl_addr_gp10b;
1595 *num_entries = ARRAY_SIZE(wl_addr_gp10b);
1596}
1597
1598static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch)
1599{
1600 int ret = 0;
1601
1602 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
1603
1604 ret = gk20a_disable_channel_tsg(g, fault_ch);
1605 if (ret) {
1606 gk20a_err(dev_from_gk20a(g),
1607 "CILP: failed to disable channel/TSG!\n");
1608 return ret;
1609 }
1610
1611 ret = g->ops.fifo.update_runlist(g, fault_ch->runlist_id, ~0, true, false);
1612 if (ret) {
1613 gk20a_err(dev_from_gk20a(g),
1614 "CILP: failed to restart runlist 0!");
1615 return ret;
1616 }
1617
1618 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist");
1619
1620 if (gk20a_is_channel_marked_as_tsg(fault_ch))
1621 gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true);
1622 else
1623 gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false);
1624
1625 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted the channel/tsg");
1626
1627 return ret;
1628}
1629
1630static int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch)
1631{
1632 int ret;
1633 struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx;
1634
1635 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
1636
1637 if (!gr_ctx)
1638 return -EINVAL;
1639
1640 if (gr_ctx->t18x.cilp_preempt_pending) {
1641 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1642 "CILP is already pending for chid %d",
1643 fault_ch->hw_chid);
1644 return 0;
1645 }
1646
1647 /* get ctx_id from the ucode image */
1648 if (!gr_ctx->t18x.ctx_id_valid) {
1649 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1650 "CILP: looking up ctx id");
1651 ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id);
1652 if (ret) {
1653 gk20a_err(dev_from_gk20a(g), "CILP: error looking up ctx id!\n");
1654 return ret;
1655 }
1656 gr_ctx->t18x.ctx_id_valid = true;
1657 }
1658
1659 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1660 "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id);
1661
1662 /* send ucode method to set ctxsw interrupt */
1663 ret = gr_gk20a_submit_fecs_sideband_method_op(g,
1664 (struct fecs_method_op_gk20a) {
1665 .method.data = gr_ctx->t18x.ctx_id,
1666 .method.addr =
1667 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(),
1668 .mailbox = {
1669 .id = 1 /* sideband */, .data = 0,
1670 .clr = ~0, .ret = NULL,
1671 .ok = gr_fecs_ctxsw_mailbox_value_pass_v(),
1672 .fail = 0},
1673 .cond.ok = GR_IS_UCODE_OP_EQUAL,
1674 .cond.fail = GR_IS_UCODE_OP_SKIP});
1675
1676 if (ret) {
1677 gk20a_err(dev_from_gk20a(g),
1678 "CILP: failed to enable ctxsw interrupt!");
1679 return ret;
1680 }
1681
1682 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1683 "CILP: enabled ctxsw completion interrupt");
1684
1685 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1686 "CILP: disabling channel %d",
1687 fault_ch->hw_chid);
1688
1689 ret = gr_gp10b_disable_channel_or_tsg(g, fault_ch);
1690 if (ret) {
1691 gk20a_err(dev_from_gk20a(g),
1692 "CILP: failed to disable channel!!");
1693 return ret;
1694 }
1695
1696 /* set cilp_preempt_pending = true and record the channel */
1697 gr_ctx->t18x.cilp_preempt_pending = true;
1698 g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid;
1699
1700 if (gk20a_is_channel_marked_as_tsg(fault_ch)) {
1701 struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid];
1702
1703 gk20a_tsg_event_id_post_event(tsg,
1704 NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED);
1705 } else {
1706 gk20a_channel_event_id_post_event(fault_ch,
1707 NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED);
1708 }
1709
1710 return 0;
1711}
1712
1713static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g,
1714 struct channel_gk20a *fault_ch)
1715{
1716 struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx;
1717
1718 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
1719
1720 if (!gr_ctx)
1721 return -EINVAL;
1722
1723 /* The ucode is self-clearing, so all we need to do here is
1724 to clear cilp_preempt_pending. */
1725 if (!gr_ctx->t18x.cilp_preempt_pending) {
1726 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1727 "CILP is already cleared for chid %d\n",
1728 fault_ch->hw_chid);
1729 return 0;
1730 }
1731
1732 gr_ctx->t18x.cilp_preempt_pending = false;
1733 g->gr.t18x.cilp_preempt_pending_chid = -1;
1734
1735 return 0;
1736}
1737
1738/* @brief pre-process work on the SM exceptions to determine if we clear them or not.
1739 *
1740 * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing
1741 */
1742static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
1743 u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr,
1744 bool sm_debugger_attached, struct channel_gk20a *fault_ch,
1745 bool *early_exit, bool *ignore_debugger)
1746{
1747 int ret;
1748 bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode ==
1749 NVGPU_COMPUTE_PREEMPTION_MODE_CILP) ;
1750 u32 global_mask = 0, dbgr_control0, global_esr_copy;
1751 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
1752 u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
1753 u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
1754
1755 *early_exit = false;
1756 *ignore_debugger = false;
1757
1758 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n",
1759 gpc, tpc, global_esr);
1760
1761 if (cilp_enabled && sm_debugger_attached) {
1762 if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f())
1763 gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
1764 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f());
1765
1766 if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f())
1767 gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
1768 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f());
1769
1770 global_mask = gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() |
1771 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() |
1772 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() |
1773 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f() |
1774 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f() |
1775 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f();
1776
1777 if (warp_esr != 0 || (global_esr & global_mask) != 0) {
1778 *ignore_debugger = true;
1779
1780 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1781 "CILP: starting wait for LOCKED_DOWN on gpc %d tpc %d\n",
1782 gpc, tpc);
1783
1784 if (gk20a_dbg_gpu_broadcast_stop_trigger(fault_ch)) {
1785 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1786 "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n",
1787 gpc, tpc);
1788 gk20a_suspend_all_sms(g, global_mask, false);
1789
1790 gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch);
1791 } else {
1792 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1793 "CILP: STOP_TRIGGER from gpc %d tpc %d\n",
1794 gpc, tpc);
1795 gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true);
1796 }
1797
1798 /* reset the HWW errors after locking down */
1799 global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset);
1800 gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy);
1801 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1802 "CILP: HWWs cleared for gpc %d tpc %d\n",
1803 gpc, tpc);
1804
1805 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n");
1806 ret = gr_gp10b_set_cilp_preempt_pending(g, fault_ch);
1807 if (ret) {
1808 gk20a_err(dev_from_gk20a(g), "CILP: error while setting CILP preempt pending!\n");
1809 return ret;
1810 }
1811
1812 dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset);
1813 if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) {
1814 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1815 "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n",
1816 gpc, tpc);
1817 dbgr_control0 = set_field(dbgr_control0,
1818 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(),
1819 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f());
1820 gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
1821 }
1822
1823 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1824 "CILP: resume for gpc %d tpc %d\n",
1825 gpc, tpc);
1826 gk20a_resume_single_sm(g, gpc, tpc);
1827
1828 *ignore_debugger = true;
1829 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc);
1830 }
1831
1832 *early_exit = true;
1833 }
1834 return 0;
1835}
1836
1837static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid)
1838{
1839 struct gr_ctx_desc *gr_ctx;
1840 struct channel_gk20a *ch;
1841 int chid;
1842 int ret = -EINVAL;
1843
1844 chid = g->gr.t18x.cilp_preempt_pending_chid;
1845
1846 ch = gk20a_channel_get(gk20a_fifo_channel_from_hw_chid(g, chid));
1847 if (!ch)
1848 return ret;
1849
1850 gr_ctx = ch->ch_ctx.gr_ctx;
1851
1852 if (gr_ctx->t18x.cilp_preempt_pending) {
1853 *__chid = chid;
1854 ret = 0;
1855 }
1856
1857 gk20a_channel_put(ch);
1858
1859 return ret;
1860}
1861
1862static int gr_gp10b_handle_fecs_error(struct gk20a *g,
1863 struct channel_gk20a *__ch,
1864 struct gr_gk20a_isr_data *isr_data)
1865{
1866 u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
1867 struct channel_gk20a *ch;
1868 int chid = -1;
1869 int ret = 0;
1870
1871 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
1872
1873 /*
1874 * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR)
1875 * indicates that a CILP ctxsw save has finished
1876 */
1877 if (gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) {
1878 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1879 "CILP: ctxsw save completed!\n");
1880
1881 /* now clear the interrupt */
1882 gk20a_writel(g, gr_fecs_host_int_clear_r(),
1883 gr_fecs_host_int_clear_ctxsw_intr1_clear_f());
1884
1885 ret = gr_gp10b_get_cilp_preempt_pending_chid(g, &chid);
1886 if (ret)
1887 goto clean_up;
1888
1889 ch = gk20a_channel_get(
1890 gk20a_fifo_channel_from_hw_chid(g, chid));
1891 if (!ch)
1892 goto clean_up;
1893
1894
1895 /* set preempt_pending to false */
1896 ret = gr_gp10b_clear_cilp_preempt_pending(g, ch);
1897 if (ret) {
1898 gk20a_err(dev_from_gk20a(g), "CILP: error while unsetting CILP preempt pending!\n");
1899 gk20a_channel_put(ch);
1900 goto clean_up;
1901 }
1902
1903 /* Post events to UMD */
1904 gk20a_dbg_gpu_post_events(ch);
1905
1906 if (gk20a_is_channel_marked_as_tsg(ch)) {
1907 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
1908
1909 gk20a_tsg_event_id_post_event(tsg,
1910 NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE);
1911 } else {
1912 gk20a_channel_event_id_post_event(ch,
1913 NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE);
1914 }
1915
1916 gk20a_channel_put(ch);
1917 }
1918
1919clean_up:
1920 /* handle any remaining interrupts */
1921 return gk20a_gr_handle_fecs_error(g, __ch, isr_data);
1922}
1923
1924static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr)
1925{
1926 if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m()))
1927 hww_warp_esr = set_field(hww_warp_esr,
1928 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(),
1929 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f());
1930
1931 return hww_warp_esr;
1932}
1933
1934static u32 get_ecc_override_val(struct gk20a *g)
1935{
1936 u32 val;
1937
1938 tegra_fuse_readl(FUSE_OPT_ECC_EN, &val);
1939 if (val)
1940 return gk20a_readl(g, gr_fecs_feature_override_ecc_r());
1941
1942 return 0;
1943}
1944
1945static bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
1946 bool *cilp_preempt_pending)
1947{
1948 struct gk20a *g = ch->g;
1949 struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx;
1950 struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
1951 bool ctx_resident = false;
1952 int err = 0;
1953
1954 *cilp_preempt_pending = false;
1955
1956 if (gk20a_is_channel_ctx_resident(ch)) {
1957 gk20a_suspend_all_sms(g, 0, false);
1958
1959 if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) {
1960 err = gr_gp10b_set_cilp_preempt_pending(g, ch);
1961 if (err)
1962 gk20a_err(dev_from_gk20a(g),
1963 "unable to set CILP preempt pending\n");
1964 else
1965 *cilp_preempt_pending = true;
1966
1967 gk20a_resume_all_sms(g);
1968 }
1969
1970 ctx_resident = true;
1971 } else {
1972 gk20a_disable_channel_tsg(g, ch);
1973 }
1974
1975 return ctx_resident;
1976}
1977
1978static int gr_gp10b_suspend_contexts(struct gk20a *g,
1979 struct dbg_session_gk20a *dbg_s,
1980 int *ctx_resident_ch_fd)
1981{
1982 u32 delay = GR_IDLE_CHECK_DEFAULT;
1983 bool cilp_preempt_pending = false;
1984 struct channel_gk20a *cilp_preempt_pending_ch = NULL;
1985 struct channel_gk20a *ch;
1986 struct dbg_session_channel_data *ch_data;
1987 int err = 0;
1988 int local_ctx_resident_ch_fd = -1;
1989 bool ctx_resident;
1990
1991 mutex_lock(&g->dbg_sessions_lock);
1992
1993 err = gr_gk20a_disable_ctxsw(g);
1994 if (err) {
1995 gk20a_err(dev_from_gk20a(g), "unable to stop gr ctxsw");
1996 mutex_unlock(&g->dbg_sessions_lock);
1997 goto clean_up;
1998 }
1999
2000 mutex_lock(&dbg_s->ch_list_lock);
2001
2002 list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry) {
2003 ch = g->fifo.channel + ch_data->chid;
2004
2005 ctx_resident = gr_gp10b_suspend_context(ch,
2006 &cilp_preempt_pending);
2007 if (ctx_resident)
2008 local_ctx_resident_ch_fd = ch_data->channel_fd;
2009 if (cilp_preempt_pending)
2010 cilp_preempt_pending_ch = ch;
2011 }
2012
2013 mutex_unlock(&dbg_s->ch_list_lock);
2014
2015 err = gr_gk20a_enable_ctxsw(g);
2016 if (err) {
2017 mutex_unlock(&g->dbg_sessions_lock);
2018 goto clean_up;
2019 }
2020
2021 mutex_unlock(&g->dbg_sessions_lock);
2022
2023 if (cilp_preempt_pending_ch) {
2024 struct channel_ctx_gk20a *ch_ctx =
2025 &cilp_preempt_pending_ch->ch_ctx;
2026 struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
2027 unsigned long end_jiffies = jiffies +
2028 msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
2029
2030 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
2031 "CILP preempt pending, waiting %lu msecs for preemption",
2032 gk20a_get_gr_idle_timeout(g));
2033
2034 do {
2035 if (!gr_ctx->t18x.cilp_preempt_pending)
2036 break;
2037
2038 usleep_range(delay, delay * 2);
2039 delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
2040 } while (time_before(jiffies, end_jiffies)
2041 || !tegra_platform_is_silicon());
2042
2043 /* If cilp is still pending at this point, timeout */
2044 if (gr_ctx->t18x.cilp_preempt_pending)
2045 err = -ETIMEDOUT;
2046 }
2047
2048 *ctx_resident_ch_fd = local_ctx_resident_ch_fd;
2049
2050clean_up:
2051 return err;
2052}
2053
2054static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
2055 u32 graphics_preempt_mode,
2056 u32 compute_preempt_mode)
2057{
2058 struct gr_ctx_desc *gr_ctx = ch->ch_ctx.gr_ctx;
2059 struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx;
2060 struct gk20a *g = ch->g;
2061 struct tsg_gk20a *tsg;
2062 struct vm_gk20a *vm;
2063 struct mem_desc *mem = &gr_ctx->mem;
2064 u32 class;
2065 int err = 0;
2066
2067 class = ch->obj_class;
2068 if (!class)
2069 return -EINVAL;
2070
2071 if (gk20a_is_channel_marked_as_tsg(ch)) {
2072 tsg = &g->fifo.tsg[ch->tsgid];
2073 vm = tsg->vm;
2074 } else {
2075 vm = ch->vm;
2076 }
2077
2078 /* skip setting anything if both modes are already set */
2079 if (graphics_preempt_mode &&
2080 (graphics_preempt_mode == gr_ctx->graphics_preempt_mode))
2081 graphics_preempt_mode = 0;
2082
2083 if (compute_preempt_mode &&
2084 (compute_preempt_mode == gr_ctx->compute_preempt_mode))
2085 compute_preempt_mode = 0;
2086
2087 if (graphics_preempt_mode == 0 && compute_preempt_mode == 0)
2088 return 0;
2089
2090 if (g->ops.gr.set_ctxsw_preemption_mode) {
2091 err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class,
2092 graphics_preempt_mode, compute_preempt_mode);
2093 if (err) {
2094 gk20a_err(dev_from_gk20a(g),
2095 "set_ctxsw_preemption_mode failed");
2096 return err;
2097 }
2098 }
2099
2100 if (gk20a_mem_begin(g, mem))
2101 return -ENOMEM;
2102
2103 err = gk20a_disable_channel_tsg(g, ch);
2104 if (err)
2105 goto unmap_ctx;
2106
2107 err = gk20a_fifo_preempt(g, ch);
2108 if (err)
2109 goto enable_ch;
2110
2111 if (g->ops.gr.update_ctxsw_preemption_mode) {
2112 g->ops.gr.update_ctxsw_preemption_mode(ch->g, ch_ctx, mem);
2113
2114 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx);
2115 if (err) {
2116 gk20a_err(dev_from_gk20a(g),
2117 "can't map patch context");
2118 goto enable_ch;
2119 }
2120 g->ops.gr.commit_global_cb_manager(g, ch, true);
2121 gr_gk20a_ctx_patch_write_end(g, ch_ctx);
2122 }
2123
2124enable_ch:
2125 gk20a_enable_channel_tsg(g, ch);
2126unmap_ctx:
2127 gk20a_mem_end(g, mem);
2128
2129 return err;
2130}
2131
2132static int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
2133 struct nvgpu_preemption_modes_rec *preemption_modes_rec)
2134{
2135 preemption_modes_rec->graphics_preemption_mode_flags = (
2136 NVGPU_GRAPHICS_PREEMPTION_MODE_WFI |
2137 NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP);
2138 preemption_modes_rec->compute_preemption_mode_flags = (
2139 NVGPU_COMPUTE_PREEMPTION_MODE_WFI |
2140 NVGPU_COMPUTE_PREEMPTION_MODE_CTA |
2141 NVGPU_COMPUTE_PREEMPTION_MODE_CILP);
2142
2143 preemption_modes_rec->default_graphics_preempt_mode =
2144 NVGPU_GRAPHICS_PREEMPTION_MODE_WFI;
2145 preemption_modes_rec->default_compute_preempt_mode =
2146 NVGPU_COMPUTE_PREEMPTION_MODE_WFI;
2147
2148 return 0;
2149}
2150static int gp10b_gr_fuse_override(struct gk20a *g)
2151{
2152 struct device_node *np = g->dev->of_node;
2153 u32 *fuses;
2154 int count, i;
2155
2156 if (!np) /* may be pcie device */
2157 return 0;
2158
2159 count = of_property_count_elems_of_size(np, "fuse-overrides", 8);
2160 if (count <= 0)
2161 return count;
2162
2163 fuses = kmalloc(sizeof(u32) * count * 2, GFP_KERNEL);
2164 if (!fuses)
2165 return -ENOMEM;
2166 of_property_read_u32_array(np, "fuse-overrides", fuses, count * 2);
2167 for (i = 0; i < count; i++) {
2168 u32 fuse, value;
2169
2170 fuse = fuses[2 * i];
2171 value = fuses[2 * i + 1];
2172 switch (fuse) {
2173 case GM20B_FUSE_OPT_TPC_DISABLE:
2174 gm20b_gr_tpc_disable_override(g, value);
2175 break;
2176 case GP10B_FUSE_OPT_ECC_EN:
2177 g->gr.t18x.fecs_feature_override_ecc_val = value;
2178 break;
2179 default:
2180 gk20a_err(dev_from_gk20a(g),
2181 "ignore unknown fuse override %08x", fuse);
2182 break;
2183 }
2184 }
2185
2186 kfree(fuses);
2187
2188 return 0;
2189}
2190
2191static int gr_gp10b_init_preemption_state(struct gk20a *g)
2192{
2193 struct gk20a_platform *platform = gk20a_get_platform(g->dev);
2194 u32 debug_2;
2195 u64 sysclk_rate;
2196 u32 sysclk_cycles;
2197
2198 sysclk_rate = platform->clk_get_rate(g->dev);
2199 sysclk_cycles = (u32)((sysclk_rate * NVGPU_GFXP_WFI_TIMEOUT_US) / 1000000ULL);
2200 gk20a_writel(g, gr_fe_gfxp_wfi_timeout_r(),
2201 gr_fe_gfxp_wfi_timeout_count_f(sysclk_cycles));
2202
2203 debug_2 = gk20a_readl(g, gr_debug_2_r());
2204 debug_2 = set_field(debug_2,
2205 gr_debug_2_gfxp_wfi_always_injects_wfi_m(),
2206 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f());
2207 gk20a_writel(g, gr_debug_2_r(), debug_2);
2208
2209 return 0;
2210}
2211
2212void gp10b_init_gr(struct gpu_ops *gops)
2213{
2214 gm20b_init_gr(gops);
2215 gops->gr.init_fs_state = gr_gp10b_init_fs_state;
2216 gops->gr.init_preemption_state = gr_gp10b_init_preemption_state;
2217 gops->gr.is_valid_class = gr_gp10b_is_valid_class;
2218 gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager;
2219 gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool;
2220 gops->gr.add_zbc_color = gr_gp10b_add_zbc_color;
2221 gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth;
2222 gops->gr.pagepool_default_size = gr_gp10b_pagepool_default_size;
2223 gops->gr.calc_global_ctx_buffer_size =
2224 gr_gp10b_calc_global_ctx_buffer_size;
2225 gops->gr.commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb;
2226 gops->gr.commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb;
2227 gops->gr.handle_sw_method = gr_gp10b_handle_sw_method;
2228 gops->gr.cb_size_default = gr_gp10b_cb_size_default;
2229 gops->gr.set_alpha_circular_buffer_size =
2230 gr_gp10b_set_alpha_circular_buffer_size;
2231 gops->gr.set_circular_buffer_size =
2232 gr_gp10b_set_circular_buffer_size;
2233 gops->gr.init_ctx_state = gr_gp10b_init_ctx_state;
2234 gops->gr.alloc_gr_ctx = gr_gp10b_alloc_gr_ctx;
2235 gops->gr.free_gr_ctx = gr_gp10b_free_gr_ctx;
2236 gops->gr.update_ctxsw_preemption_mode =
2237 gr_gp10b_update_ctxsw_preemption_mode;
2238 gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs;
2239 gops->gr.wait_empty = gr_gp10b_wait_empty;
2240 gops->gr.init_cyclestats = gr_gp10b_init_cyclestats;
2241 gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask;
2242 gops->gr.get_access_map = gr_gp10b_get_access_map;
2243 gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception;
2244 gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception;
2245 gops->gr.mask_hww_warp_esr = gp10b_mask_hww_warp_esr;
2246 gops->gr.pre_process_sm_exception =
2247 gr_gp10b_pre_process_sm_exception;
2248 gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error;
2249 gops->gr.create_gr_sysfs = gr_gp10b_create_sysfs;
2250 gops->gr.get_lrf_tex_ltc_dram_override = get_ecc_override_val;
2251 gops->gr.suspend_contexts = gr_gp10b_suspend_contexts;
2252 gops->gr.set_preemption_mode = gr_gp10b_set_preemption_mode;
2253 gops->gr.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode;
2254 gops->gr.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags;
2255 gops->gr.fuse_override = gp10b_gr_fuse_override;
2256 gops->gr.load_smid_config = gr_gp10b_load_smid_config;
2257}
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
new file mode 100644
index 00000000..5338789f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -0,0 +1,103 @@
1/*
2 * GP10B GPU GR
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_GR_GP10B_H_
17#define _NVGPU_GR_GP10B_H_
18
19#include <linux/version.h>
20
21struct gpu_ops;
22
23enum {
24 PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
25 PASCAL_A = 0xC097,
26 PASCAL_COMPUTE_A = 0xC0C0,
27 PASCAL_DMA_COPY_A = 0xC0B5,
28 PASCAL_DMA_COPY_B = 0xC1B5,
29};
30
31#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c
32#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
33#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028
34#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
35#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
36#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
37
38void gp10b_init_gr(struct gpu_ops *ops);
39int gr_gp10b_init_fs_state(struct gk20a *g);
40int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
41 struct mem_desc *mem);
42void gr_gp10b_create_sysfs(struct device *dev);
43
44struct ecc_stat {
45 char **names;
46 u32 *counters;
47 struct hlist_node hash_node;
48};
49
50struct gr_t18x {
51 struct {
52 u32 preempt_image_size;
53#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)
54 u32 force_preemption_gfxp;
55 u32 force_preemption_cilp;
56 u32 dump_ctxsw_stats_on_channel_close;
57#else
58 bool force_preemption_gfxp;
59 bool force_preemption_cilp;
60 bool dump_ctxsw_stats_on_channel_close;
61#endif
62 struct dentry *debugfs_force_preemption_cilp;
63 struct dentry *debugfs_force_preemption_gfxp;
64 struct dentry *debugfs_dump_ctxsw_stats;
65 } ctx_vars;
66
67 struct {
68 struct ecc_stat sm_lrf_single_err_count;
69 struct ecc_stat sm_lrf_double_err_count;
70
71 struct ecc_stat sm_shm_sec_count;
72 struct ecc_stat sm_shm_sed_count;
73 struct ecc_stat sm_shm_ded_count;
74
75 struct ecc_stat tex_total_sec_pipe0_count;
76 struct ecc_stat tex_total_ded_pipe0_count;
77 struct ecc_stat tex_unique_sec_pipe0_count;
78 struct ecc_stat tex_unique_ded_pipe0_count;
79 struct ecc_stat tex_total_sec_pipe1_count;
80 struct ecc_stat tex_total_ded_pipe1_count;
81 struct ecc_stat tex_unique_sec_pipe1_count;
82 struct ecc_stat tex_unique_ded_pipe1_count;
83
84 struct ecc_stat l2_sec_count;
85 struct ecc_stat l2_ded_count;
86 } ecc_stats;
87
88 u32 fecs_feature_override_ecc_val;
89
90 int cilp_preempt_pending_chid;
91};
92
93struct gr_ctx_desc_t18x {
94 struct mem_desc preempt_ctxsw_buffer;
95 struct mem_desc spill_ctxsw_buffer;
96 struct mem_desc betacb_ctxsw_buffer;
97 struct mem_desc pagepool_ctxsw_buffer;
98 u32 ctx_id;
99 bool ctx_id_valid;
100 bool cilp_preempt_pending;
101};
102
103#endif
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h
new file mode 100644
index 00000000..c3277017
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h
@@ -0,0 +1,28 @@
1/*
2 * GP10B GPU graphics ops
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _GR_OPS_GP10B_H_
17#define _GR_OPS_GP10B_H_
18
19#include "gr_ops.h"
20
21#define __gr_gp10b_op(X) gr_gp10b_ ## X
22#define __set_gr_gp10b_op(X) . X = gr_gp10b_ ## X
23
24bool __gr_gp10b_op(is_valid_class)(struct gk20a *, u32);
25int __gr_gp10b_op(alloc_obj_ctx)(struct channel_gk20a *, struct nvgpu_alloc_obj_ctx_args *);
26
27
28#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
new file mode 100644
index 00000000..a656f10d
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -0,0 +1,269 @@
1/*
2 * GP10B Tegra HAL interface
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/printk.h>
18#include <linux/version.h>
19
20#include <linux/types.h>
21
22#include "gk20a/gk20a.h"
23
24#include "gp10b/gr_gp10b.h"
25#include "gp10b/fecs_trace_gp10b.h"
26#include "gp10b/mc_gp10b.h"
27#include "gp10b/ltc_gp10b.h"
28#include "gp10b/mm_gp10b.h"
29#include "gp10b/ce_gp10b.h"
30#include "gp10b/fb_gp10b.h"
31#include "gp10b/pmu_gp10b.h"
32#include "gp10b/gr_ctx_gp10b.h"
33#include "gp10b/fifo_gp10b.h"
34#include "gp10b/gp10b_gating_reglist.h"
35#include "gp10b/regops_gp10b.h"
36#include "gp10b/cde_gp10b.h"
37#include "gp10b/therm_gp10b.h"
38
39#include "gm20b/gr_gm20b.h"
40#include "gm20b/fifo_gm20b.h"
41#include "gm20b/pmu_gm20b.h"
42#include "gm20b/clk_gm20b.h"
43#include <linux/tegra-fuse.h>
44
45#include "gp10b.h"
46#include "hw_proj_gp10b.h"
47#include "gk20a/dbg_gpu_gk20a.h"
48#include "gk20a/css_gr_gk20a.h"
49
50#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
51#define FUSE_OPT_PRIV_SEC_EN_0 0x264
52#endif
53#define PRIV_SECURITY_ENABLED 0x01
54
55static struct gpu_ops gp10b_ops = {
56 .clock_gating = {
57 .slcg_bus_load_gating_prod =
58 gp10b_slcg_bus_load_gating_prod,
59 .slcg_ce2_load_gating_prod =
60 gp10b_slcg_ce2_load_gating_prod,
61 .slcg_chiplet_load_gating_prod =
62 gp10b_slcg_chiplet_load_gating_prod,
63 .slcg_ctxsw_firmware_load_gating_prod =
64 gp10b_slcg_ctxsw_firmware_load_gating_prod,
65 .slcg_fb_load_gating_prod =
66 gp10b_slcg_fb_load_gating_prod,
67 .slcg_fifo_load_gating_prod =
68 gp10b_slcg_fifo_load_gating_prod,
69 .slcg_gr_load_gating_prod =
70 gr_gp10b_slcg_gr_load_gating_prod,
71 .slcg_ltc_load_gating_prod =
72 ltc_gp10b_slcg_ltc_load_gating_prod,
73 .slcg_perf_load_gating_prod =
74 gp10b_slcg_perf_load_gating_prod,
75 .slcg_priring_load_gating_prod =
76 gp10b_slcg_priring_load_gating_prod,
77 .slcg_pmu_load_gating_prod =
78 gp10b_slcg_pmu_load_gating_prod,
79 .slcg_therm_load_gating_prod =
80 gp10b_slcg_therm_load_gating_prod,
81 .slcg_xbar_load_gating_prod =
82 gp10b_slcg_xbar_load_gating_prod,
83 .blcg_bus_load_gating_prod =
84 gp10b_blcg_bus_load_gating_prod,
85 .blcg_ce_load_gating_prod =
86 gp10b_blcg_ce_load_gating_prod,
87 .blcg_ctxsw_firmware_load_gating_prod =
88 gp10b_blcg_ctxsw_firmware_load_gating_prod,
89 .blcg_fb_load_gating_prod =
90 gp10b_blcg_fb_load_gating_prod,
91 .blcg_fifo_load_gating_prod =
92 gp10b_blcg_fifo_load_gating_prod,
93 .blcg_gr_load_gating_prod =
94 gp10b_blcg_gr_load_gating_prod,
95 .blcg_ltc_load_gating_prod =
96 gp10b_blcg_ltc_load_gating_prod,
97 .blcg_pwr_csb_load_gating_prod =
98 gp10b_blcg_pwr_csb_load_gating_prod,
99 .blcg_pmu_load_gating_prod =
100 gp10b_blcg_pmu_load_gating_prod,
101 .blcg_xbar_load_gating_prod =
102 gp10b_blcg_xbar_load_gating_prod,
103 .pg_gr_load_gating_prod =
104 gr_gp10b_pg_gr_load_gating_prod,
105 }
106};
107
108static int gp10b_get_litter_value(struct gk20a *g, int value)
109{
110 int ret = EINVAL;
111 switch (value) {
112 case GPU_LIT_NUM_GPCS:
113 ret = proj_scal_litter_num_gpcs_v();
114 break;
115 case GPU_LIT_NUM_PES_PER_GPC:
116 ret = proj_scal_litter_num_pes_per_gpc_v();
117 break;
118 case GPU_LIT_NUM_ZCULL_BANKS:
119 ret = proj_scal_litter_num_zcull_banks_v();
120 break;
121 case GPU_LIT_NUM_TPC_PER_GPC:
122 ret = proj_scal_litter_num_tpc_per_gpc_v();
123 break;
124 case GPU_LIT_NUM_FBPS:
125 ret = proj_scal_litter_num_fbps_v();
126 break;
127 case GPU_LIT_GPC_BASE:
128 ret = proj_gpc_base_v();
129 break;
130 case GPU_LIT_GPC_STRIDE:
131 ret = proj_gpc_stride_v();
132 break;
133 case GPU_LIT_GPC_SHARED_BASE:
134 ret = proj_gpc_shared_base_v();
135 break;
136 case GPU_LIT_TPC_IN_GPC_BASE:
137 ret = proj_tpc_in_gpc_base_v();
138 break;
139 case GPU_LIT_TPC_IN_GPC_STRIDE:
140 ret = proj_tpc_in_gpc_stride_v();
141 break;
142 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
143 ret = proj_tpc_in_gpc_shared_base_v();
144 break;
145 case GPU_LIT_PPC_IN_GPC_BASE:
146 ret = proj_ppc_in_gpc_base_v();
147 break;
148 case GPU_LIT_PPC_IN_GPC_STRIDE:
149 ret = proj_ppc_in_gpc_stride_v();
150 break;
151 case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
152 ret = proj_ppc_in_gpc_shared_base_v();
153 break;
154 case GPU_LIT_ROP_BASE:
155 ret = proj_rop_base_v();
156 break;
157 case GPU_LIT_ROP_STRIDE:
158 ret = proj_rop_stride_v();
159 break;
160 case GPU_LIT_ROP_SHARED_BASE:
161 ret = proj_rop_shared_base_v();
162 break;
163 case GPU_LIT_HOST_NUM_ENGINES:
164 ret = proj_host_num_engines_v();
165 break;
166 case GPU_LIT_HOST_NUM_PBDMA:
167 ret = proj_host_num_pbdma_v();
168 break;
169 case GPU_LIT_LTC_STRIDE:
170 ret = proj_ltc_stride_v();
171 break;
172 case GPU_LIT_LTS_STRIDE:
173 ret = proj_lts_stride_v();
174 break;
175 /* GP10B does not have a FBPA unit, despite what's listed in the
176 * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS,
177 * so hardcode all values to 0.
178 */
179 case GPU_LIT_NUM_FBPAS:
180 case GPU_LIT_FBPA_STRIDE:
181 case GPU_LIT_FBPA_BASE:
182 case GPU_LIT_FBPA_SHARED_BASE:
183 ret = 0;
184 break;
185 default:
186 gk20a_err(dev_from_gk20a(g), "Missing definition %d", value);
187 BUG();
188 break;
189 }
190
191 return ret;
192}
193
194int gp10b_init_hal(struct gk20a *g)
195{
196 struct gpu_ops *gops = &g->ops;
197 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
198 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
199 u32 val;
200
201 *gops = gp10b_ops;
202 gops->pmupstate = false;
203#ifdef CONFIG_TEGRA_ACR
204 if (platform->is_fmodel) {
205 gops->privsecurity = 0;
206 gops->securegpccs = 0;
207 } else {
208 tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val);
209 if (val & PRIV_SECURITY_ENABLED) {
210 gops->privsecurity = 1;
211 gops->securegpccs =1;
212 } else {
213 gk20a_dbg_info("priv security is disabled in HW");
214 gops->privsecurity = 0;
215 gops->securegpccs = 0;
216 }
217 }
218#else
219 if (platform->is_fmodel) {
220 gk20a_dbg_info("running simulator with PRIV security disabled");
221 gops->privsecurity = 0;
222 gops->securegpccs = 0;
223 } else {
224 tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val);
225 if (val & PRIV_SECURITY_ENABLED) {
226 gk20a_dbg_info("priv security is not supported but enabled");
227 gops->privsecurity = 1;
228 gops->securegpccs =1;
229 return -EPERM;
230 } else {
231 gops->privsecurity = 0;
232 gops->securegpccs = 0;
233 }
234 }
235#endif
236
237 gp10b_init_mc(gops);
238 gp10b_init_gr(gops);
239 gp10b_init_fecs_trace_ops(gops);
240 gp10b_init_ltc(gops);
241 gp10b_init_fb(gops);
242 gp10b_init_fifo(gops);
243 gp10b_init_ce(gops);
244 gp10b_init_gr_ctx(gops);
245 gp10b_init_mm(gops);
246 gp10b_init_pmu_ops(gops);
247 gk20a_init_debug_ops(gops);
248 gk20a_init_dbg_session_ops(gops);
249 gp10b_init_regops(gops);
250 gp10b_init_cde_ops(gops);
251 gp10b_init_therm_ops(gops);
252 gk20a_init_tsg_ops(gops);
253#if defined(CONFIG_GK20A_CYCLE_STATS)
254 gk20a_init_css_ops(gops);
255#endif
256 gops->name = "gp10b";
257 gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics;
258 gops->get_litter_value = gp10b_get_litter_value;
259 gops->read_ptimer = gk20a_read_ptimer;
260
261 c->twod_class = FERMI_TWOD_A;
262 c->threed_class = PASCAL_A;
263 c->compute_class = PASCAL_COMPUTE_A;
264 c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
265 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
266 c->dma_copy_class = PASCAL_DMA_COPY_A;
267
268 return 0;
269}
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
new file mode 100644
index 00000000..0b464d07
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
@@ -0,0 +1,21 @@
1/*
2 * GP10B Tegra HAL interface
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_HAL_GP10B_H
17#define _NVGPU_HAL_GP10B_H
18struct gk20a;
19
20int gp10b_init_hal(struct gk20a *gops);
21#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h
new file mode 100644
index 00000000..02c06610
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h
@@ -0,0 +1,217 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_bus_gp10b_h_
51#define _hw_bus_gp10b_h_
52
53static inline u32 bus_bar0_window_r(void)
54{
55 return 0x00001700;
56}
57static inline u32 bus_bar0_window_base_f(u32 v)
58{
59 return (v & 0xffffff) << 0;
60}
61static inline u32 bus_bar0_window_target_vid_mem_f(void)
62{
63 return 0x0;
64}
65static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
66{
67 return 0x2000000;
68}
69static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
70{
71 return 0x3000000;
72}
73static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
74{
75 return 0x00000010;
76}
77static inline u32 bus_bar1_block_r(void)
78{
79 return 0x00001704;
80}
81static inline u32 bus_bar1_block_ptr_f(u32 v)
82{
83 return (v & 0xfffffff) << 0;
84}
85static inline u32 bus_bar1_block_target_vid_mem_f(void)
86{
87 return 0x0;
88}
89static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
90{
91 return 0x20000000;
92}
93static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
94{
95 return 0x30000000;
96}
97static inline u32 bus_bar1_block_mode_virtual_f(void)
98{
99 return 0x80000000;
100}
101static inline u32 bus_bar2_block_r(void)
102{
103 return 0x00001714;
104}
105static inline u32 bus_bar2_block_ptr_f(u32 v)
106{
107 return (v & 0xfffffff) << 0;
108}
109static inline u32 bus_bar2_block_target_vid_mem_f(void)
110{
111 return 0x0;
112}
113static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
114{
115 return 0x20000000;
116}
117static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
118{
119 return 0x30000000;
120}
121static inline u32 bus_bar2_block_mode_virtual_f(void)
122{
123 return 0x80000000;
124}
125static inline u32 bus_bar1_block_ptr_shift_v(void)
126{
127 return 0x0000000c;
128}
129static inline u32 bus_bar2_block_ptr_shift_v(void)
130{
131 return 0x0000000c;
132}
133static inline u32 bus_bind_status_r(void)
134{
135 return 0x00001710;
136}
137static inline u32 bus_bind_status_bar1_pending_v(u32 r)
138{
139 return (r >> 0) & 0x1;
140}
141static inline u32 bus_bind_status_bar1_pending_empty_f(void)
142{
143 return 0x0;
144}
145static inline u32 bus_bind_status_bar1_pending_busy_f(void)
146{
147 return 0x1;
148}
149static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
150{
151 return (r >> 1) & 0x1;
152}
153static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
154{
155 return 0x0;
156}
157static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
158{
159 return 0x2;
160}
161static inline u32 bus_bind_status_bar2_pending_v(u32 r)
162{
163 return (r >> 2) & 0x1;
164}
165static inline u32 bus_bind_status_bar2_pending_empty_f(void)
166{
167 return 0x0;
168}
169static inline u32 bus_bind_status_bar2_pending_busy_f(void)
170{
171 return 0x4;
172}
173static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
174{
175 return (r >> 3) & 0x1;
176}
177static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
178{
179 return 0x0;
180}
181static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
182{
183 return 0x8;
184}
185static inline u32 bus_intr_0_r(void)
186{
187 return 0x00001100;
188}
189static inline u32 bus_intr_0_pri_squash_m(void)
190{
191 return 0x1 << 1;
192}
193static inline u32 bus_intr_0_pri_fecserr_m(void)
194{
195 return 0x1 << 2;
196}
197static inline u32 bus_intr_0_pri_timeout_m(void)
198{
199 return 0x1 << 3;
200}
201static inline u32 bus_intr_en_0_r(void)
202{
203 return 0x00001140;
204}
205static inline u32 bus_intr_en_0_pri_squash_m(void)
206{
207 return 0x1 << 1;
208}
209static inline u32 bus_intr_en_0_pri_fecserr_m(void)
210{
211 return 0x1 << 2;
212}
213static inline u32 bus_intr_en_0_pri_timeout_m(void)
214{
215 return 0x1 << 3;
216}
217#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h
new file mode 100644
index 00000000..99398961
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h
@@ -0,0 +1,117 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ccsr_gp10b_h_
51#define _hw_ccsr_gp10b_h_
52
53static inline u32 ccsr_channel_inst_r(u32 i)
54{
55 return 0x00800000 + i*8;
56}
57static inline u32 ccsr_channel_inst__size_1_v(void)
58{
59 return 0x00000200;
60}
61static inline u32 ccsr_channel_inst_ptr_f(u32 v)
62{
63 return (v & 0xfffffff) << 0;
64}
65static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
66{
67 return 0x0;
68}
69static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
70{
71 return 0x20000000;
72}
73static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
74{
75 return 0x30000000;
76}
77static inline u32 ccsr_channel_inst_bind_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 ccsr_channel_inst_bind_true_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 ccsr_channel_r(u32 i)
86{
87 return 0x00800004 + i*8;
88}
89static inline u32 ccsr_channel__size_1_v(void)
90{
91 return 0x00000200;
92}
93static inline u32 ccsr_channel_enable_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 ccsr_channel_enable_set_f(u32 v)
98{
99 return (v & 0x1) << 10;
100}
101static inline u32 ccsr_channel_enable_set_true_f(void)
102{
103 return 0x400;
104}
105static inline u32 ccsr_channel_enable_clr_true_f(void)
106{
107 return 0x800;
108}
109static inline u32 ccsr_channel_status_v(u32 r)
110{
111 return (r >> 24) & 0xf;
112}
113static inline u32 ccsr_channel_busy_v(u32 r)
114{
115 return (r >> 28) & 0x1;
116}
117#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ce_gp10b.h
new file mode 100644
index 00000000..3f6e1470
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_ce_gp10b.h
@@ -0,0 +1,81 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ce_gp10b_h_
51#define _hw_ce_gp10b_h_
52
53static inline u32 ce_intr_status_r(u32 i)
54{
55 return 0x00104410 + i*128;
56}
57static inline u32 ce_intr_status_blockpipe_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 ce_intr_status_blockpipe_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 ce_intr_status_launcherr_pending_f(void)
74{
75 return 0x4;
76}
77static inline u32 ce_intr_status_launcherr_reset_f(void)
78{
79 return 0x4;
80}
81#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h
new file mode 100644
index 00000000..640453ce
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_chiplet_pwr_gp10b_h_
51#define _hw_chiplet_pwr_gp10b_h_
52
53static inline u32 chiplet_pwr_gpcs_weight_6_r(void)
54{
55 return 0x0010e018;
56}
57static inline u32 chiplet_pwr_gpcs_weight_7_r(void)
58{
59 return 0x0010e01c;
60}
61static inline u32 chiplet_pwr_gpcs_config_1_r(void)
62{
63 return 0x0010e03c;
64}
65static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void)
66{
67 return 0x1;
68}
69static inline u32 chiplet_pwr_fbps_weight_0_r(void)
70{
71 return 0x0010e100;
72}
73static inline u32 chiplet_pwr_fbps_weight_1_r(void)
74{
75 return 0x0010e104;
76}
77static inline u32 chiplet_pwr_fbps_config_1_r(void)
78{
79 return 0x0010e13c;
80}
81static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void)
82{
83 return 0x1;
84}
85#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h
new file mode 100644
index 00000000..eef9a96f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h
@@ -0,0 +1,473 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ctxsw_prog_gp10b_h_
51#define _hw_ctxsw_prog_gp10b_h_
52
53static inline u32 ctxsw_prog_fecs_header_v(void)
54{
55 return 0x00000100;
56}
57static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
58{
59 return 0x00000008;
60}
61static inline u32 ctxsw_prog_main_image_patch_count_o(void)
62{
63 return 0x00000010;
64}
65static inline u32 ctxsw_prog_main_image_context_id_o(void)
66{
67 return 0x000000f0;
68}
69static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
70{
71 return 0x00000014;
72}
73static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
74{
75 return 0x00000018;
76}
77static inline u32 ctxsw_prog_main_image_zcull_o(void)
78{
79 return 0x0000001c;
80}
81static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
82{
83 return 0x00000001;
84}
85static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
86{
87 return 0x00000002;
88}
89static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
90{
91 return 0x00000020;
92}
93static inline u32 ctxsw_prog_main_image_pm_o(void)
94{
95 return 0x00000028;
96}
97static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
98{
99 return 0x7 << 0;
100}
101static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
102{
103 return 0x0;
104}
105static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
106{
107 return 0x7 << 3;
108}
109static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
110{
111 return 0x8;
112}
113static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
114{
115 return 0x0;
116}
117static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
118{
119 return 0x0000002c;
120}
121static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
122{
123 return 0x000000f4;
124}
125static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
126{
127 return 0x000000d0;
128}
129static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
130{
131 return 0x000000d4;
132}
133static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
134{
135 return 0x000000d8;
136}
137static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
138{
139 return 0x000000dc;
140}
141static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
142{
143 return 0x000000f8;
144}
145static inline u32 ctxsw_prog_main_image_magic_value_o(void)
146{
147 return 0x000000fc;
148}
149static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
150{
151 return 0x600dc0de;
152}
153static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
154{
155 return 0x0000000c;
156}
157static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
158{
159 return (r >> 0) & 0xffff;
160}
161static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
162{
163 return 0x000000f4;
164}
165static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
166{
167 return (r >> 0) & 0xffff;
168}
169static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
170{
171 return (r >> 16) & 0xffff;
172}
173static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
174{
175 return 0x000000f8;
176}
177static inline u32 ctxsw_prog_local_magic_value_o(void)
178{
179 return 0x000000fc;
180}
181static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
182{
183 return 0xad0becab;
184}
185static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
186{
187 return 0x000000ec;
188}
189static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
190{
191 return (r >> 0) & 0xffff;
192}
193static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
194{
195 return (r >> 16) & 0xff;
196}
197static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
198{
199 return 0x00000100;
200}
201static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
202{
203 return 0x00000004;
204}
205static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
206{
207 return 0x00000000;
208}
209static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
210{
211 return 0x00000002;
212}
213static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
214{
215 return 0x000000a0;
216}
217static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
218{
219 return 2;
220}
221static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
222{
223 return (v & 0x3) << 0;
224}
225static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
226{
227 return 0x3 << 0;
228}
229static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
230{
231 return (r >> 0) & 0x3;
232}
233static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
234{
235 return 0x0;
236}
237static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
238{
239 return 0x2;
240}
241static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
242{
243 return 0x000000a4;
244}
245static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
246{
247 return 0x000000a8;
248}
249static inline u32 ctxsw_prog_main_image_misc_options_o(void)
250{
251 return 0x0000003c;
252}
253static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
254{
255 return 0x1 << 3;
256}
257static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
258{
259 return 0x0;
260}
261static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
262{
263 return 0x00000080;
264}
265static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
266{
267 return (v & 0x3) << 0;
268}
269static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
270{
271 return 0x1;
272}
273static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
274{
275 return 0x00000068;
276}
277static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
278{
279 return 0x00000084;
280}
281static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
282{
283 return (v & 0x3) << 0;
284}
285static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
286{
287 return 0x1;
288}
289static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
290{
291 return 0x2;
292}
293static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
294{
295 return 0x000000ac;
296}
297static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
298{
299 return (v & 0xffff) << 0;
300}
301static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
302{
303 return 0x000000b0;
304}
305static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
306{
307 return 0xfffffff << 0;
308}
309static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
310{
311 return 0x3 << 28;
312}
313static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
314{
315 return 0x0;
316}
317static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
318{
319 return 0x20000000;
320}
321static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
322{
323 return 0x30000000;
324}
325static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
326{
327 return 0x000000b4;
328}
329static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
330{
331 return (v & 0xffffffff) << 0;
332}
333static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
334{
335 return 0x00000080;
336}
337static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
338{
339 return 0x00000020;
340}
341static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
342{
343 return 0x00000000;
344}
345static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
346{
347 return 0x00000000;
348}
349static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
350{
351 return 0x00000004;
352}
353static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
354{
355 return 0x600dbeef;
356}
357static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
358{
359 return 0x00000008;
360}
361static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
362{
363 return 0x0000000c;
364}
365static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
366{
367 return 0x00000018;
368}
369static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
370{
371 return 0x0000001c;
372}
373static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
374{
375 return (v & 0xffffff) << 0;
376}
377static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
378{
379 return (r >> 0) & 0xffffff;
380}
381static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
382{
383 return (v & 0xff) << 24;
384}
385static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
386{
387 return 0xff << 24;
388}
389static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
390{
391 return (r >> 24) & 0xff;
392}
393static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
394{
395 return 0x00000001;
396}
397static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
398{
399 return 0x1000000;
400}
401static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
402{
403 return 0x00000002;
404}
405static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
406{
407 return 0x2000000;
408}
409static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
410{
411 return 0x0000000a;
412}
413static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
414{
415 return 0xa000000;
416}
417static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
418{
419 return 0x0000000b;
420}
421static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
422{
423 return 0xb000000;
424}
425static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
426{
427 return 0x0000000c;
428}
429static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
430{
431 return 0xc000000;
432}
433static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
434{
435 return 0x0000000d;
436}
437static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
438{
439 return 0xd000000;
440}
441static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
442{
443 return 0x00000003;
444}
445static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
446{
447 return 0x3000000;
448}
449static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
450{
451 return 0x00000004;
452}
453static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
454{
455 return 0x4000000;
456}
457static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
458{
459 return 0x00000005;
460}
461static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
462{
463 return 0x5000000;
464}
465static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
466{
467 return 0x000000ff;
468}
469static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
470{
471 return 0xff000000;
472}
473#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h
new file mode 100644
index 00000000..ec340777
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h
@@ -0,0 +1,481 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fb_gp10b_h_
51#define _hw_fb_gp10b_h_
52
53static inline u32 fb_fbhub_num_active_ltcs_r(void)
54{
55 return 0x00100800;
56}
57static inline u32 fb_mmu_ctrl_r(void)
58{
59 return 0x00100c80;
60}
61static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
62{
63 return (v & 0x1) << 0;
64}
65static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
66{
67 return 0x0;
68}
69static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
70{
71 return 0x1;
72}
73static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
74{
75 return (r >> 15) & 0x1;
76}
77static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
82{
83 return (r >> 16) & 0xff;
84}
85static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
86{
87 return (r >> 11) & 0x1;
88}
89static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
90{
91 return 0x800;
92}
93static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
94{
95 return 0x0;
96}
97static inline u32 fb_priv_mmu_phy_secure_r(void)
98{
99 return 0x00100ce4;
100}
101static inline u32 fb_mmu_invalidate_pdb_r(void)
102{
103 return 0x00100cb8;
104}
105static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
106{
107 return 0x0;
108}
109static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
110{
111 return 0x2;
112}
113static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
114{
115 return (v & 0xfffffff) << 4;
116}
117static inline u32 fb_mmu_invalidate_r(void)
118{
119 return 0x00100cbc;
120}
121static inline u32 fb_mmu_invalidate_all_va_true_f(void)
122{
123 return 0x1;
124}
125static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
126{
127 return 0x2;
128}
129static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
130{
131 return 1;
132}
133static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
134{
135 return (v & 0x1) << 2;
136}
137static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
138{
139 return 0x1 << 2;
140}
141static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
142{
143 return (r >> 2) & 0x1;
144}
145static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
146{
147 return 0x4;
148}
149static inline u32 fb_mmu_invalidate_replay_s(void)
150{
151 return 3;
152}
153static inline u32 fb_mmu_invalidate_replay_f(u32 v)
154{
155 return (v & 0x7) << 3;
156}
157static inline u32 fb_mmu_invalidate_replay_m(void)
158{
159 return 0x7 << 3;
160}
161static inline u32 fb_mmu_invalidate_replay_v(u32 r)
162{
163 return (r >> 3) & 0x7;
164}
165static inline u32 fb_mmu_invalidate_replay_none_f(void)
166{
167 return 0x0;
168}
169static inline u32 fb_mmu_invalidate_replay_start_f(void)
170{
171 return 0x8;
172}
173static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
174{
175 return 0x10;
176}
177static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
178{
179 return 0x18;
180}
181static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
182{
183 return 0x20;
184}
185static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
186{
187 return 0x20;
188}
189static inline u32 fb_mmu_invalidate_sys_membar_s(void)
190{
191 return 1;
192}
193static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
194{
195 return (v & 0x1) << 6;
196}
197static inline u32 fb_mmu_invalidate_sys_membar_m(void)
198{
199 return 0x1 << 6;
200}
201static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
202{
203 return (r >> 6) & 0x1;
204}
205static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
206{
207 return 0x40;
208}
209static inline u32 fb_mmu_invalidate_ack_s(void)
210{
211 return 2;
212}
213static inline u32 fb_mmu_invalidate_ack_f(u32 v)
214{
215 return (v & 0x3) << 7;
216}
217static inline u32 fb_mmu_invalidate_ack_m(void)
218{
219 return 0x3 << 7;
220}
221static inline u32 fb_mmu_invalidate_ack_v(u32 r)
222{
223 return (r >> 7) & 0x3;
224}
225static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
226{
227 return 0x0;
228}
229static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
230{
231 return 0x100;
232}
233static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
234{
235 return 0x80;
236}
237static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
238{
239 return 6;
240}
241static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
242{
243 return (v & 0x3f) << 9;
244}
245static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
246{
247 return 0x3f << 9;
248}
249static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
250{
251 return (r >> 9) & 0x3f;
252}
253static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
254{
255 return 5;
256}
257static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
258{
259 return (v & 0x1f) << 15;
260}
261static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
262{
263 return 0x1f << 15;
264}
265static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
266{
267 return (r >> 15) & 0x1f;
268}
269static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
270{
271 return 1;
272}
273static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
274{
275 return (v & 0x1) << 20;
276}
277static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
278{
279 return 0x1 << 20;
280}
281static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
282{
283 return (r >> 20) & 0x1;
284}
285static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
286{
287 return 0x0;
288}
289static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
290{
291 return 0x100000;
292}
293static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
294{
295 return 3;
296}
297static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
298{
299 return (v & 0x7) << 24;
300}
301static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
302{
303 return 0x7 << 24;
304}
305static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
306{
307 return (r >> 24) & 0x7;
308}
309static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
310{
311 return 0x0;
312}
313static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
314{
315 return 0x1000000;
316}
317static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
318{
319 return 0x2000000;
320}
321static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
322{
323 return 0x3000000;
324}
325static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
326{
327 return 0x4000000;
328}
329static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
330{
331 return 0x5000000;
332}
333static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
334{
335 return 0x6000000;
336}
337static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
338{
339 return 0x7000000;
340}
341static inline u32 fb_mmu_invalidate_trigger_s(void)
342{
343 return 1;
344}
345static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
346{
347 return (v & 0x1) << 31;
348}
349static inline u32 fb_mmu_invalidate_trigger_m(void)
350{
351 return 0x1 << 31;
352}
353static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
354{
355 return (r >> 31) & 0x1;
356}
357static inline u32 fb_mmu_invalidate_trigger_true_f(void)
358{
359 return 0x80000000;
360}
361static inline u32 fb_mmu_debug_wr_r(void)
362{
363 return 0x00100cc8;
364}
365static inline u32 fb_mmu_debug_wr_aperture_s(void)
366{
367 return 2;
368}
369static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
370{
371 return (v & 0x3) << 0;
372}
373static inline u32 fb_mmu_debug_wr_aperture_m(void)
374{
375 return 0x3 << 0;
376}
377static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
378{
379 return (r >> 0) & 0x3;
380}
381static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
382{
383 return 0x0;
384}
385static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
386{
387 return 0x2;
388}
389static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
390{
391 return 0x3;
392}
393static inline u32 fb_mmu_debug_wr_vol_false_f(void)
394{
395 return 0x0;
396}
397static inline u32 fb_mmu_debug_wr_vol_true_v(void)
398{
399 return 0x00000001;
400}
401static inline u32 fb_mmu_debug_wr_vol_true_f(void)
402{
403 return 0x4;
404}
405static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
406{
407 return (v & 0xfffffff) << 4;
408}
409static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
410{
411 return 0x0000000c;
412}
413static inline u32 fb_mmu_debug_rd_r(void)
414{
415 return 0x00100ccc;
416}
417static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
418{
419 return 0x0;
420}
421static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
422{
423 return 0x2;
424}
425static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
426{
427 return 0x3;
428}
429static inline u32 fb_mmu_debug_rd_vol_false_f(void)
430{
431 return 0x0;
432}
433static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
434{
435 return (v & 0xfffffff) << 4;
436}
437static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
438{
439 return 0x0000000c;
440}
441static inline u32 fb_mmu_debug_ctrl_r(void)
442{
443 return 0x00100cc4;
444}
445static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
446{
447 return (r >> 16) & 0x1;
448}
449static inline u32 fb_mmu_debug_ctrl_debug_m(void)
450{
451 return 0x1 << 16;
452}
453static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
454{
455 return 0x00000001;
456}
457static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
458{
459 return 0x00000000;
460}
461static inline u32 fb_mmu_vpr_info_r(void)
462{
463 return 0x00100cd0;
464}
465static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
466{
467 return (r >> 2) & 0x1;
468}
469static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
470{
471 return 0x00000000;
472}
473static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
474{
475 return 0x00000001;
476}
477static inline u32 fb_niso_flush_sysmem_addr_r(void)
478{
479 return 0x00100c10;
480}
481#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h
new file mode 100644
index 00000000..8370d4c6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h
@@ -0,0 +1,689 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fifo_gp10b_h_
51#define _hw_fifo_gp10b_h_
52
53static inline u32 fifo_bar1_base_r(void)
54{
55 return 0x00002254;
56}
57static inline u32 fifo_bar1_base_ptr_f(u32 v)
58{
59 return (v & 0xfffffff) << 0;
60}
61static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
62{
63 return 0x0000000c;
64}
65static inline u32 fifo_bar1_base_valid_false_f(void)
66{
67 return 0x0;
68}
69static inline u32 fifo_bar1_base_valid_true_f(void)
70{
71 return 0x10000000;
72}
73static inline u32 fifo_runlist_base_r(void)
74{
75 return 0x00002270;
76}
77static inline u32 fifo_runlist_base_ptr_f(u32 v)
78{
79 return (v & 0xfffffff) << 0;
80}
81static inline u32 fifo_runlist_base_target_vid_mem_f(void)
82{
83 return 0x0;
84}
85static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
86{
87 return 0x20000000;
88}
89static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
90{
91 return 0x30000000;
92}
93static inline u32 fifo_runlist_r(void)
94{
95 return 0x00002274;
96}
97static inline u32 fifo_runlist_engine_f(u32 v)
98{
99 return (v & 0xf) << 20;
100}
101static inline u32 fifo_eng_runlist_base_r(u32 i)
102{
103 return 0x00002280 + i*8;
104}
105static inline u32 fifo_eng_runlist_base__size_1_v(void)
106{
107 return 0x00000001;
108}
109static inline u32 fifo_eng_runlist_r(u32 i)
110{
111 return 0x00002284 + i*8;
112}
113static inline u32 fifo_eng_runlist__size_1_v(void)
114{
115 return 0x00000001;
116}
117static inline u32 fifo_eng_runlist_length_f(u32 v)
118{
119 return (v & 0xffff) << 0;
120}
121static inline u32 fifo_eng_runlist_length_max_v(void)
122{
123 return 0x0000ffff;
124}
125static inline u32 fifo_eng_runlist_pending_true_f(void)
126{
127 return 0x100000;
128}
129static inline u32 fifo_pb_timeslice_r(u32 i)
130{
131 return 0x00002350 + i*4;
132}
133static inline u32 fifo_pb_timeslice_timeout_16_f(void)
134{
135 return 0x10;
136}
137static inline u32 fifo_pb_timeslice_timescale_0_f(void)
138{
139 return 0x0;
140}
141static inline u32 fifo_pb_timeslice_enable_true_f(void)
142{
143 return 0x10000000;
144}
145static inline u32 fifo_pbdma_map_r(u32 i)
146{
147 return 0x00002390 + i*4;
148}
149static inline u32 fifo_intr_0_r(void)
150{
151 return 0x00002100;
152}
153static inline u32 fifo_intr_0_bind_error_pending_f(void)
154{
155 return 0x1;
156}
157static inline u32 fifo_intr_0_bind_error_reset_f(void)
158{
159 return 0x1;
160}
161static inline u32 fifo_intr_0_sched_error_pending_f(void)
162{
163 return 0x100;
164}
165static inline u32 fifo_intr_0_sched_error_reset_f(void)
166{
167 return 0x100;
168}
169static inline u32 fifo_intr_0_chsw_error_pending_f(void)
170{
171 return 0x10000;
172}
173static inline u32 fifo_intr_0_chsw_error_reset_f(void)
174{
175 return 0x10000;
176}
177static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
178{
179 return 0x800000;
180}
181static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
182{
183 return 0x800000;
184}
185static inline u32 fifo_intr_0_lb_error_pending_f(void)
186{
187 return 0x1000000;
188}
189static inline u32 fifo_intr_0_lb_error_reset_f(void)
190{
191 return 0x1000000;
192}
193static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
194{
195 return 0x2000000;
196}
197static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
198{
199 return 0x8000000;
200}
201static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
202{
203 return 0x8000000;
204}
205static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
206{
207 return 0x10000000;
208}
209static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
210{
211 return 0x20000000;
212}
213static inline u32 fifo_intr_0_runlist_event_pending_f(void)
214{
215 return 0x40000000;
216}
217static inline u32 fifo_intr_0_channel_intr_pending_f(void)
218{
219 return 0x80000000;
220}
221static inline u32 fifo_intr_en_0_r(void)
222{
223 return 0x00002140;
224}
225static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
226{
227 return (v & 0x1) << 8;
228}
229static inline u32 fifo_intr_en_0_sched_error_m(void)
230{
231 return 0x1 << 8;
232}
233static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
234{
235 return (v & 0x1) << 28;
236}
237static inline u32 fifo_intr_en_0_mmu_fault_m(void)
238{
239 return 0x1 << 28;
240}
241static inline u32 fifo_intr_en_1_r(void)
242{
243 return 0x00002528;
244}
245static inline u32 fifo_intr_bind_error_r(void)
246{
247 return 0x0000252c;
248}
249static inline u32 fifo_intr_sched_error_r(void)
250{
251 return 0x0000254c;
252}
253static inline u32 fifo_intr_sched_error_code_f(u32 v)
254{
255 return (v & 0xff) << 0;
256}
257static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
258{
259 return 0x0000000a;
260}
261static inline u32 fifo_intr_chsw_error_r(void)
262{
263 return 0x0000256c;
264}
265static inline u32 fifo_intr_mmu_fault_id_r(void)
266{
267 return 0x0000259c;
268}
269static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
270{
271 return 0x00000000;
272}
273static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
274{
275 return 0x0;
276}
277static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
278{
279 return 0x00002800 + i*16;
280}
281static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
282{
283 return (r >> 0) & 0xfffffff;
284}
285static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
286{
287 return 0x0000000c;
288}
289static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
290{
291 return 0x00002804 + i*16;
292}
293static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
294{
295 return 0x00002808 + i*16;
296}
297static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
298{
299 return 0x0000280c + i*16;
300}
301static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
302{
303 return (r >> 0) & 0x1f;
304}
305static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
306{
307 return (r >> 20) & 0x1;
308}
309static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
310{
311 return 0x00000000;
312}
313static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
314{
315 return 0x00000001;
316}
317static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
318{
319 return (r >> 8) & 0x7f;
320}
321static inline u32 fifo_intr_pbdma_id_r(void)
322{
323 return 0x000025a0;
324}
325static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
326{
327 return (v & 0x1) << (0 + i*1);
328}
329static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
330{
331 return (r >> (0 + i*1)) & 0x1;
332}
333static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
334{
335 return 0x00000001;
336}
337static inline u32 fifo_intr_runlist_r(void)
338{
339 return 0x00002a00;
340}
341static inline u32 fifo_fb_timeout_r(void)
342{
343 return 0x00002a04;
344}
345static inline u32 fifo_fb_timeout_period_m(void)
346{
347 return 0x3fffffff << 0;
348}
349static inline u32 fifo_fb_timeout_period_max_f(void)
350{
351 return 0x3fffffff;
352}
353static inline u32 fifo_error_sched_disable_r(void)
354{
355 return 0x0000262c;
356}
357static inline u32 fifo_sched_disable_r(void)
358{
359 return 0x00002630;
360}
361static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
362{
363 return (v & 0x1) << (0 + i*1);
364}
365static inline u32 fifo_sched_disable_runlist_m(u32 i)
366{
367 return 0x1 << (0 + i*1);
368}
369static inline u32 fifo_sched_disable_true_v(void)
370{
371 return 0x00000001;
372}
373static inline u32 fifo_preempt_r(void)
374{
375 return 0x00002634;
376}
377static inline u32 fifo_preempt_pending_true_f(void)
378{
379 return 0x100000;
380}
381static inline u32 fifo_preempt_type_channel_f(void)
382{
383 return 0x0;
384}
385static inline u32 fifo_preempt_type_tsg_f(void)
386{
387 return 0x1000000;
388}
389static inline u32 fifo_preempt_chid_f(u32 v)
390{
391 return (v & 0xfff) << 0;
392}
393static inline u32 fifo_preempt_id_f(u32 v)
394{
395 return (v & 0xfff) << 0;
396}
397static inline u32 fifo_trigger_mmu_fault_r(u32 i)
398{
399 return 0x00002a30 + i*4;
400}
401static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
402{
403 return (v & 0x1f) << 0;
404}
405static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
406{
407 return (v & 0x1) << 8;
408}
409static inline u32 fifo_engine_status_r(u32 i)
410{
411 return 0x00002640 + i*8;
412}
413static inline u32 fifo_engine_status__size_1_v(void)
414{
415 return 0x00000002;
416}
417static inline u32 fifo_engine_status_id_v(u32 r)
418{
419 return (r >> 0) & 0xfff;
420}
421static inline u32 fifo_engine_status_id_type_v(u32 r)
422{
423 return (r >> 12) & 0x1;
424}
425static inline u32 fifo_engine_status_id_type_chid_v(void)
426{
427 return 0x00000000;
428}
429static inline u32 fifo_engine_status_id_type_tsgid_v(void)
430{
431 return 0x00000001;
432}
433static inline u32 fifo_engine_status_ctx_status_v(u32 r)
434{
435 return (r >> 13) & 0x7;
436}
437static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
438{
439 return 0x00000000;
440}
441static inline u32 fifo_engine_status_ctx_status_valid_v(void)
442{
443 return 0x00000001;
444}
445static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
446{
447 return 0x00000005;
448}
449static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
450{
451 return 0x00000006;
452}
453static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
454{
455 return 0x00000007;
456}
457static inline u32 fifo_engine_status_next_id_v(u32 r)
458{
459 return (r >> 16) & 0xfff;
460}
461static inline u32 fifo_engine_status_next_id_type_v(u32 r)
462{
463 return (r >> 28) & 0x1;
464}
465static inline u32 fifo_engine_status_next_id_type_chid_v(void)
466{
467 return 0x00000000;
468}
469static inline u32 fifo_engine_status_faulted_v(u32 r)
470{
471 return (r >> 30) & 0x1;
472}
473static inline u32 fifo_engine_status_faulted_true_v(void)
474{
475 return 0x00000001;
476}
477static inline u32 fifo_engine_status_engine_v(u32 r)
478{
479 return (r >> 31) & 0x1;
480}
481static inline u32 fifo_engine_status_engine_idle_v(void)
482{
483 return 0x00000000;
484}
485static inline u32 fifo_engine_status_engine_busy_v(void)
486{
487 return 0x00000001;
488}
489static inline u32 fifo_engine_status_ctxsw_v(u32 r)
490{
491 return (r >> 15) & 0x1;
492}
493static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
494{
495 return 0x00000001;
496}
497static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
498{
499 return 0x8000;
500}
501static inline u32 fifo_pbdma_status_r(u32 i)
502{
503 return 0x00003080 + i*4;
504}
505static inline u32 fifo_pbdma_status__size_1_v(void)
506{
507 return 0x00000001;
508}
509static inline u32 fifo_pbdma_status_id_v(u32 r)
510{
511 return (r >> 0) & 0xfff;
512}
513static inline u32 fifo_pbdma_status_id_type_v(u32 r)
514{
515 return (r >> 12) & 0x1;
516}
517static inline u32 fifo_pbdma_status_id_type_chid_v(void)
518{
519 return 0x00000000;
520}
521static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
522{
523 return 0x00000001;
524}
525static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
526{
527 return (r >> 13) & 0x7;
528}
529static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
530{
531 return 0x00000001;
532}
533static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
534{
535 return 0x00000005;
536}
537static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
538{
539 return 0x00000006;
540}
541static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
542{
543 return 0x00000007;
544}
545static inline u32 fifo_pbdma_status_next_id_v(u32 r)
546{
547 return (r >> 16) & 0xfff;
548}
549static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
550{
551 return (r >> 28) & 0x1;
552}
553static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
554{
555 return 0x00000000;
556}
557static inline u32 fifo_pbdma_status_chsw_v(u32 r)
558{
559 return (r >> 15) & 0x1;
560}
561static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
562{
563 return 0x00000001;
564}
565static inline u32 fifo_replay_fault_buffer_lo_r(void)
566{
567 return 0x00002a70;
568}
569static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
570{
571 return (r >> 0) & 0x1;
572}
573static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
574{
575 return 0x00000001;
576}
577static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
578{
579 return 0x00000000;
580}
581static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
582{
583 return (v & 0xfffff) << 12;
584}
585static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
586{
587 return 0x00000000;
588}
589static inline u32 fifo_replay_fault_buffer_hi_r(void)
590{
591 return 0x00002a74;
592}
593static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
594{
595 return (v & 0xff) << 0;
596}
597static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
598{
599 return 0x00000000;
600}
601static inline u32 fifo_replay_fault_buffer_size_r(void)
602{
603 return 0x00002a78;
604}
605static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
606{
607 return (v & 0x1ff) << 0;
608}
609static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
610{
611 return 0x000000c0;
612}
613static inline u32 fifo_replay_fault_buffer_get_r(void)
614{
615 return 0x00002a7c;
616}
617static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
618{
619 return (v & 0x1ff) << 0;
620}
621static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
622{
623 return 0x00000000;
624}
625static inline u32 fifo_replay_fault_buffer_put_r(void)
626{
627 return 0x00002a80;
628}
629static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
630{
631 return (v & 0x1ff) << 0;
632}
633static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
634{
635 return 0x00000000;
636}
637static inline u32 fifo_replay_fault_buffer_info_r(void)
638{
639 return 0x00002a84;
640}
641static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
642{
643 return (v & 0x1) << 0;
644}
645static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
646{
647 return 0x00000000;
648}
649static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
650{
651 return 0x00000001;
652}
653static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
654{
655 return 0x00000001;
656}
657static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
658{
659 return (v & 0x1) << 24;
660}
661static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
662{
663 return 0x00000000;
664}
665static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
666{
667 return 0x00000001;
668}
669static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
670{
671 return 0x00000001;
672}
673static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
674{
675 return (v & 0x1) << 28;
676}
677static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
678{
679 return 0x00000000;
680}
681static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
682{
683 return 0x00000001;
684}
685static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
686{
687 return 0x00000001;
688}
689#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h
new file mode 100644
index 00000000..e2dff490
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h
@@ -0,0 +1,181 @@
1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_flush_gp10b_h_
51#define _hw_flush_gp10b_h_
52
53static inline u32 flush_l2_system_invalidate_r(void)
54{
55 return 0x00070004;
56}
57static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
58{
59 return (r >> 0) & 0x1;
60}
61static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
66{
67 return 0x1;
68}
69static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
70{
71 return (r >> 1) & 0x1;
72}
73static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
74{
75 return 0x00000001;
76}
77static inline u32 flush_l2_flush_dirty_r(void)
78{
79 return 0x00070010;
80}
81static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
82{
83 return (r >> 0) & 0x1;
84}
85static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
86{
87 return 0x00000000;
88}
89static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
90{
91 return 0x0;
92}
93static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
94{
95 return 0x00000001;
96}
97static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
98{
99 return 0x1;
100}
101static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
102{
103 return (r >> 1) & 0x1;
104}
105static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
106{
107 return 0x00000000;
108}
109static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
110{
111 return 0x0;
112}
113static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
114{
115 return 0x00000001;
116}
117static inline u32 flush_l2_clean_comptags_r(void)
118{
119 return 0x0007000c;
120}
121static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
122{
123 return (r >> 0) & 0x1;
124}
125static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
126{
127 return 0x00000000;
128}
129static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
130{
131 return 0x0;
132}
133static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
138{
139 return 0x1;
140}
141static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
142{
143 return (r >> 1) & 0x1;
144}
145static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
146{
147 return 0x00000000;
148}
149static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
150{
151 return 0x0;
152}
153static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
154{
155 return 0x00000001;
156}
157static inline u32 flush_fb_flush_r(void)
158{
159 return 0x00070000;
160}
161static inline u32 flush_fb_flush_pending_v(u32 r)
162{
163 return (r >> 0) & 0x1;
164}
165static inline u32 flush_fb_flush_pending_busy_v(void)
166{
167 return 0x00000001;
168}
169static inline u32 flush_fb_flush_pending_busy_f(void)
170{
171 return 0x1;
172}
173static inline u32 flush_fb_flush_outstanding_v(u32 r)
174{
175 return (r >> 1) & 0x1;
176}
177static inline u32 flush_fb_flush_outstanding_true_v(void)
178{
179 return 0x00000001;
180}
181#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h
new file mode 100644
index 00000000..2b1acf2f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fuse_gp10b_h_
51#define _hw_fuse_gp10b_h_
52
53static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
54{
55 return 0x00021c38 + i*4;
56}
57static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
58{
59 return 0x00021838 + i*4;
60}
61static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
62{
63 return 0x00021944;
64}
65static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
66{
67 return (v & 0xff) << 0;
68}
69static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
70{
71 return 0xff << 0;
72}
73static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
74{
75 return (r >> 0) & 0xff;
76}
77static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
78{
79 return 0x00021948;
80}
81static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
82{
83 return (v & 0x1) << 0;
84}
85static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
86{
87 return 0x1 << 0;
88}
89static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
90{
91 return (r >> 0) & 0x1;
92}
93static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
94{
95 return 0x1;
96}
97static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
98{
99 return 0x0;
100}
101static inline u32 fuse_status_opt_fbio_r(void)
102{
103 return 0x00021c14;
104}
105static inline u32 fuse_status_opt_fbio_data_f(u32 v)
106{
107 return (v & 0xffff) << 0;
108}
109static inline u32 fuse_status_opt_fbio_data_m(void)
110{
111 return 0xffff << 0;
112}
113static inline u32 fuse_status_opt_fbio_data_v(u32 r)
114{
115 return (r >> 0) & 0xffff;
116}
117static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
118{
119 return 0x00021d70 + i*4;
120}
121static inline u32 fuse_status_opt_fbp_r(void)
122{
123 return 0x00021d38;
124}
125static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
126{
127 return (r >> (0 + i*0)) & 0x1;
128}
129static inline u32 fuse_opt_ecc_en_r(void)
130{
131 return 0x00021228;
132}
133static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
134{
135 return 0x000213f0;
136}
137static inline u32 fuse_opt_sec_debug_en_r(void)
138{
139 return 0x00021218;
140}
141static inline u32 fuse_opt_priv_sec_en_r(void)
142{
143 return 0x00021434;
144}
145#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
new file mode 100644
index 00000000..d231ee44
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
@@ -0,0 +1,1277 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gmmu_gp10b_h_
51#define _hw_gmmu_gp10b_h_
52
53static inline u32 gmmu_new_pde_is_pte_w(void)
54{
55 return 0;
56}
57static inline u32 gmmu_new_pde_is_pte_false_f(void)
58{
59 return 0x0;
60}
61static inline u32 gmmu_new_pde_aperture_w(void)
62{
63 return 0;
64}
65static inline u32 gmmu_new_pde_aperture_invalid_f(void)
66{
67 return 0x0;
68}
69static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
70{
71 return 0x2;
72}
73static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
74{
75 return 0x4;
76}
77static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
78{
79 return 0x6;
80}
81static inline u32 gmmu_new_pde_address_sys_f(u32 v)
82{
83 return (v & 0xfffffff) << 8;
84}
85static inline u32 gmmu_new_pde_address_sys_w(void)
86{
87 return 0;
88}
89static inline u32 gmmu_new_pde_vol_w(void)
90{
91 return 0;
92}
93static inline u32 gmmu_new_pde_vol_true_f(void)
94{
95 return 0x8;
96}
97static inline u32 gmmu_new_pde_vol_false_f(void)
98{
99 return 0x0;
100}
101static inline u32 gmmu_new_pde_address_shift_v(void)
102{
103 return 0x0000000c;
104}
105static inline u32 gmmu_new_pde__size_v(void)
106{
107 return 0x00000008;
108}
109static inline u32 gmmu_new_dual_pde_is_pte_w(void)
110{
111 return 0;
112}
113static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
114{
115 return 0x0;
116}
117static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
118{
119 return 0;
120}
121static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
122{
123 return 0x0;
124}
125static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
126{
127 return 0x2;
128}
129static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
130{
131 return 0x4;
132}
133static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
134{
135 return 0x6;
136}
137static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
138{
139 return (v & 0xfffffff) << 4;
140}
141static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
142{
143 return 0;
144}
145static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
146{
147 return 2;
148}
149static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
150{
151 return 0x0;
152}
153static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
154{
155 return 0x2;
156}
157static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
158{
159 return 0x4;
160}
161static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
162{
163 return 0x6;
164}
165static inline u32 gmmu_new_dual_pde_vol_small_w(void)
166{
167 return 2;
168}
169static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
170{
171 return 0x8;
172}
173static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
174{
175 return 0x0;
176}
177static inline u32 gmmu_new_dual_pde_vol_big_w(void)
178{
179 return 0;
180}
181static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
182{
183 return 0x8;
184}
185static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
186{
187 return 0x0;
188}
189static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
190{
191 return (v & 0xfffffff) << 8;
192}
193static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
194{
195 return 2;
196}
197static inline u32 gmmu_new_dual_pde_address_shift_v(void)
198{
199 return 0x0000000c;
200}
201static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
202{
203 return 0x00000008;
204}
205static inline u32 gmmu_new_dual_pde__size_v(void)
206{
207 return 0x00000010;
208}
209static inline u32 gmmu_new_pte__size_v(void)
210{
211 return 0x00000008;
212}
213static inline u32 gmmu_new_pte_valid_w(void)
214{
215 return 0;
216}
217static inline u32 gmmu_new_pte_valid_true_f(void)
218{
219 return 0x1;
220}
221static inline u32 gmmu_new_pte_valid_false_f(void)
222{
223 return 0x0;
224}
225static inline u32 gmmu_new_pte_privilege_w(void)
226{
227 return 0;
228}
229static inline u32 gmmu_new_pte_privilege_true_f(void)
230{
231 return 0x20;
232}
233static inline u32 gmmu_new_pte_privilege_false_f(void)
234{
235 return 0x0;
236}
237static inline u32 gmmu_new_pte_address_sys_f(u32 v)
238{
239 return (v & 0xfffffff) << 8;
240}
241static inline u32 gmmu_new_pte_address_sys_w(void)
242{
243 return 0;
244}
245static inline u32 gmmu_new_pte_address_vid_f(u32 v)
246{
247 return (v & 0xffffff) << 8;
248}
249static inline u32 gmmu_new_pte_address_vid_w(void)
250{
251 return 0;
252}
253static inline u32 gmmu_new_pte_vol_w(void)
254{
255 return 0;
256}
257static inline u32 gmmu_new_pte_vol_true_f(void)
258{
259 return 0x8;
260}
261static inline u32 gmmu_new_pte_vol_false_f(void)
262{
263 return 0x0;
264}
265static inline u32 gmmu_new_pte_aperture_w(void)
266{
267 return 0;
268}
269static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
270{
271 return 0x0;
272}
273static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
274{
275 return 0x4;
276}
277static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
278{
279 return 0x6;
280}
281static inline u32 gmmu_new_pte_read_only_w(void)
282{
283 return 0;
284}
285static inline u32 gmmu_new_pte_read_only_true_f(void)
286{
287 return 0x40;
288}
289static inline u32 gmmu_new_pte_comptagline_f(u32 v)
290{
291 return (v & 0x3ffff) << 4;
292}
293static inline u32 gmmu_new_pte_comptagline_w(void)
294{
295 return 1;
296}
297static inline u32 gmmu_new_pte_kind_f(u32 v)
298{
299 return (v & 0xff) << 24;
300}
301static inline u32 gmmu_new_pte_kind_w(void)
302{
303 return 1;
304}
305static inline u32 gmmu_new_pte_address_shift_v(void)
306{
307 return 0x0000000c;
308}
309static inline u32 gmmu_pte_kind_f(u32 v)
310{
311 return (v & 0xff) << 4;
312}
313static inline u32 gmmu_pte_kind_w(void)
314{
315 return 1;
316}
317static inline u32 gmmu_pte_kind_invalid_v(void)
318{
319 return 0x000000ff;
320}
321static inline u32 gmmu_pte_kind_pitch_v(void)
322{
323 return 0x00000000;
324}
325static inline u32 gmmu_pte_kind_z16_v(void)
326{
327 return 0x00000001;
328}
329static inline u32 gmmu_pte_kind_z16_2c_v(void)
330{
331 return 0x00000002;
332}
333static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
334{
335 return 0x00000003;
336}
337static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
338{
339 return 0x00000004;
340}
341static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
342{
343 return 0x00000005;
344}
345static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
346{
347 return 0x00000006;
348}
349static inline u32 gmmu_pte_kind_z16_2z_v(void)
350{
351 return 0x00000007;
352}
353static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
354{
355 return 0x00000008;
356}
357static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
358{
359 return 0x00000009;
360}
361static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
362{
363 return 0x0000000a;
364}
365static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
366{
367 return 0x0000000b;
368}
369static inline u32 gmmu_pte_kind_z16_2cz_v(void)
370{
371 return 0x00000036;
372}
373static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
374{
375 return 0x00000037;
376}
377static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
378{
379 return 0x00000038;
380}
381static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
382{
383 return 0x00000039;
384}
385static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
386{
387 return 0x0000005f;
388}
389static inline u32 gmmu_pte_kind_z16_4cz_v(void)
390{
391 return 0x0000000c;
392}
393static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
394{
395 return 0x0000000d;
396}
397static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
398{
399 return 0x0000000e;
400}
401static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
402{
403 return 0x0000000f;
404}
405static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
406{
407 return 0x00000010;
408}
409static inline u32 gmmu_pte_kind_s8z24_v(void)
410{
411 return 0x00000011;
412}
413static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
414{
415 return 0x00000012;
416}
417static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
418{
419 return 0x00000013;
420}
421static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
422{
423 return 0x00000014;
424}
425static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
426{
427 return 0x00000015;
428}
429static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
430{
431 return 0x00000016;
432}
433static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
434{
435 return 0x00000017;
436}
437static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
438{
439 return 0x00000018;
440}
441static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
442{
443 return 0x00000019;
444}
445static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
446{
447 return 0x0000001a;
448}
449static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
450{
451 return 0x0000001b;
452}
453static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
454{
455 return 0x0000001c;
456}
457static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
458{
459 return 0x0000001d;
460}
461static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
462{
463 return 0x0000001e;
464}
465static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
466{
467 return 0x0000001f;
468}
469static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
470{
471 return 0x00000020;
472}
473static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
474{
475 return 0x00000021;
476}
477static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
478{
479 return 0x00000022;
480}
481static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
482{
483 return 0x00000023;
484}
485static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
486{
487 return 0x00000024;
488}
489static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
490{
491 return 0x00000025;
492}
493static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
494{
495 return 0x00000026;
496}
497static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
498{
499 return 0x00000027;
500}
501static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
502{
503 return 0x00000028;
504}
505static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
506{
507 return 0x00000029;
508}
509static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
510{
511 return 0x0000002e;
512}
513static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
514{
515 return 0x0000002f;
516}
517static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
518{
519 return 0x00000030;
520}
521static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
522{
523 return 0x00000031;
524}
525static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
526{
527 return 0x00000032;
528}
529static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
530{
531 return 0x00000033;
532}
533static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
534{
535 return 0x00000034;
536}
537static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
538{
539 return 0x00000035;
540}
541static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
542{
543 return 0x0000003a;
544}
545static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
546{
547 return 0x0000003b;
548}
549static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
550{
551 return 0x0000003c;
552}
553static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
554{
555 return 0x0000003d;
556}
557static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
558{
559 return 0x0000003e;
560}
561static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
562{
563 return 0x0000003f;
564}
565static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
566{
567 return 0x00000040;
568}
569static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
570{
571 return 0x00000041;
572}
573static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
574{
575 return 0x00000042;
576}
577static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
578{
579 return 0x00000043;
580}
581static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
582{
583 return 0x00000044;
584}
585static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
586{
587 return 0x00000045;
588}
589static inline u32 gmmu_pte_kind_z24s8_v(void)
590{
591 return 0x00000046;
592}
593static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
594{
595 return 0x00000047;
596}
597static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
598{
599 return 0x00000048;
600}
601static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
602{
603 return 0x00000049;
604}
605static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
606{
607 return 0x0000004a;
608}
609static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
610{
611 return 0x0000004b;
612}
613static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
614{
615 return 0x0000004c;
616}
617static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
618{
619 return 0x0000004d;
620}
621static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
622{
623 return 0x0000004e;
624}
625static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
626{
627 return 0x0000004f;
628}
629static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
630{
631 return 0x00000050;
632}
633static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
634{
635 return 0x00000051;
636}
637static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
638{
639 return 0x00000052;
640}
641static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
642{
643 return 0x00000053;
644}
645static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
646{
647 return 0x00000054;
648}
649static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
650{
651 return 0x00000055;
652}
653static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
654{
655 return 0x00000056;
656}
657static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
658{
659 return 0x00000057;
660}
661static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
662{
663 return 0x00000058;
664}
665static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
666{
667 return 0x00000059;
668}
669static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
670{
671 return 0x0000005a;
672}
673static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
674{
675 return 0x0000005b;
676}
677static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
678{
679 return 0x0000005c;
680}
681static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
682{
683 return 0x0000005d;
684}
685static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
686{
687 return 0x0000005e;
688}
689static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
690{
691 return 0x00000063;
692}
693static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
694{
695 return 0x00000064;
696}
697static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
698{
699 return 0x00000065;
700}
701static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
702{
703 return 0x00000066;
704}
705static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
706{
707 return 0x00000067;
708}
709static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
710{
711 return 0x00000068;
712}
713static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
714{
715 return 0x00000069;
716}
717static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
718{
719 return 0x0000006a;
720}
721static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
722{
723 return 0x0000006f;
724}
725static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
726{
727 return 0x00000070;
728}
729static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
730{
731 return 0x00000071;
732}
733static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
734{
735 return 0x00000072;
736}
737static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
738{
739 return 0x00000073;
740}
741static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
742{
743 return 0x00000074;
744}
745static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
746{
747 return 0x00000075;
748}
749static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
750{
751 return 0x00000076;
752}
753static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
754{
755 return 0x00000077;
756}
757static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
758{
759 return 0x00000078;
760}
761static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
762{
763 return 0x00000079;
764}
765static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
766{
767 return 0x0000007a;
768}
769static inline u32 gmmu_pte_kind_zf32_v(void)
770{
771 return 0x0000007b;
772}
773static inline u32 gmmu_pte_kind_zf32_1z_v(void)
774{
775 return 0x0000007c;
776}
777static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
778{
779 return 0x0000007d;
780}
781static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
782{
783 return 0x0000007e;
784}
785static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
786{
787 return 0x0000007f;
788}
789static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
790{
791 return 0x00000080;
792}
793static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
794{
795 return 0x00000081;
796}
797static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
798{
799 return 0x00000082;
800}
801static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
802{
803 return 0x00000083;
804}
805static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
806{
807 return 0x00000084;
808}
809static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
810{
811 return 0x00000085;
812}
813static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
814{
815 return 0x00000086;
816}
817static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
818{
819 return 0x00000087;
820}
821static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
822{
823 return 0x00000088;
824}
825static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
826{
827 return 0x00000089;
828}
829static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
830{
831 return 0x0000008a;
832}
833static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
834{
835 return 0x0000008b;
836}
837static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
838{
839 return 0x0000008c;
840}
841static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
842{
843 return 0x0000008d;
844}
845static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
846{
847 return 0x0000008e;
848}
849static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
850{
851 return 0x0000008f;
852}
853static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
854{
855 return 0x00000090;
856}
857static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
858{
859 return 0x00000091;
860}
861static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
862{
863 return 0x00000092;
864}
865static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
866{
867 return 0x00000097;
868}
869static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
870{
871 return 0x00000098;
872}
873static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
874{
875 return 0x00000099;
876}
877static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
878{
879 return 0x0000009a;
880}
881static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
882{
883 return 0x0000009b;
884}
885static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
886{
887 return 0x0000009c;
888}
889static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
890{
891 return 0x0000009d;
892}
893static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
894{
895 return 0x0000009e;
896}
897static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
898{
899 return 0x0000009f;
900}
901static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
902{
903 return 0x000000a0;
904}
905static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
906{
907 return 0x000000a1;
908}
909static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
910{
911 return 0x000000a2;
912}
913static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
914{
915 return 0x000000a3;
916}
917static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
918{
919 return 0x000000a4;
920}
921static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
922{
923 return 0x000000a5;
924}
925static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
926{
927 return 0x000000a6;
928}
929static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
930{
931 return 0x000000a7;
932}
933static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
934{
935 return 0x000000a8;
936}
937static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
938{
939 return 0x000000a9;
940}
941static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
942{
943 return 0x000000aa;
944}
945static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
946{
947 return 0x000000ab;
948}
949static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
950{
951 return 0x000000ac;
952}
953static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
954{
955 return 0x000000ad;
956}
957static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
958{
959 return 0x000000ae;
960}
961static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
962{
963 return 0x000000b3;
964}
965static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
966{
967 return 0x000000b4;
968}
969static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
970{
971 return 0x000000b5;
972}
973static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
974{
975 return 0x000000b6;
976}
977static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
978{
979 return 0x000000b7;
980}
981static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
982{
983 return 0x000000b8;
984}
985static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
986{
987 return 0x000000b9;
988}
989static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
990{
991 return 0x000000ba;
992}
993static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
994{
995 return 0x000000bb;
996}
997static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
998{
999 return 0x000000bc;
1000}
1001static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
1002{
1003 return 0x000000bd;
1004}
1005static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
1006{
1007 return 0x000000be;
1008}
1009static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
1010{
1011 return 0x000000bf;
1012}
1013static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
1014{
1015 return 0x000000c0;
1016}
1017static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
1018{
1019 return 0x000000c1;
1020}
1021static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
1022{
1023 return 0x000000c2;
1024}
1025static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
1026{
1027 return 0x000000c3;
1028}
1029static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
1030{
1031 return 0x000000c4;
1032}
1033static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
1034{
1035 return 0x000000c5;
1036}
1037static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
1038{
1039 return 0x000000c6;
1040}
1041static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
1042{
1043 return 0x000000c7;
1044}
1045static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
1046{
1047 return 0x000000c8;
1048}
1049static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
1050{
1051 return 0x000000ce;
1052}
1053static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
1054{
1055 return 0x000000cf;
1056}
1057static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
1058{
1059 return 0x000000d0;
1060}
1061static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
1062{
1063 return 0x000000d1;
1064}
1065static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
1066{
1067 return 0x000000d2;
1068}
1069static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
1070{
1071 return 0x000000d3;
1072}
1073static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
1074{
1075 return 0x000000d4;
1076}
1077static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
1078{
1079 return 0x000000d5;
1080}
1081static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
1082{
1083 return 0x000000d6;
1084}
1085static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
1086{
1087 return 0x000000d7;
1088}
1089static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
1090{
1091 return 0x000000fe;
1092}
1093static inline u32 gmmu_pte_kind_c32_2c_v(void)
1094{
1095 return 0x000000d8;
1096}
1097static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
1098{
1099 return 0x000000d9;
1100}
1101static inline u32 gmmu_pte_kind_c32_2cba_v(void)
1102{
1103 return 0x000000da;
1104}
1105static inline u32 gmmu_pte_kind_c32_2cra_v(void)
1106{
1107 return 0x000000db;
1108}
1109static inline u32 gmmu_pte_kind_c32_2bra_v(void)
1110{
1111 return 0x000000dc;
1112}
1113static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
1114{
1115 return 0x000000dd;
1116}
1117static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
1118{
1119 return 0x000000de;
1120}
1121static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
1122{
1123 return 0x000000cc;
1124}
1125static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
1126{
1127 return 0x000000df;
1128}
1129static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
1130{
1131 return 0x000000e0;
1132}
1133static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
1134{
1135 return 0x000000e1;
1136}
1137static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
1138{
1139 return 0x000000e2;
1140}
1141static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
1142{
1143 return 0x000000e3;
1144}
1145static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
1146{
1147 return 0x0000002c;
1148}
1149static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
1150{
1151 return 0x000000e4;
1152}
1153static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
1154{
1155 return 0x000000e5;
1156}
1157static inline u32 gmmu_pte_kind_c64_2c_v(void)
1158{
1159 return 0x000000e6;
1160}
1161static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
1162{
1163 return 0x000000e7;
1164}
1165static inline u32 gmmu_pte_kind_c64_2cba_v(void)
1166{
1167 return 0x000000e8;
1168}
1169static inline u32 gmmu_pte_kind_c64_2cra_v(void)
1170{
1171 return 0x000000e9;
1172}
1173static inline u32 gmmu_pte_kind_c64_2bra_v(void)
1174{
1175 return 0x000000ea;
1176}
1177static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
1178{
1179 return 0x000000eb;
1180}
1181static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
1182{
1183 return 0x000000ec;
1184}
1185static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
1186{
1187 return 0x000000cd;
1188}
1189static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
1190{
1191 return 0x000000ed;
1192}
1193static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
1194{
1195 return 0x000000ee;
1196}
1197static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
1198{
1199 return 0x000000ef;
1200}
1201static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
1202{
1203 return 0x000000f0;
1204}
1205static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
1206{
1207 return 0x000000f1;
1208}
1209static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
1210{
1211 return 0x0000002d;
1212}
1213static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
1214{
1215 return 0x000000f2;
1216}
1217static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
1218{
1219 return 0x000000f3;
1220}
1221static inline u32 gmmu_pte_kind_c128_2c_v(void)
1222{
1223 return 0x000000f4;
1224}
1225static inline u32 gmmu_pte_kind_c128_2cr_v(void)
1226{
1227 return 0x000000f5;
1228}
1229static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
1230{
1231 return 0x000000f6;
1232}
1233static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
1234{
1235 return 0x000000f7;
1236}
1237static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
1238{
1239 return 0x000000f8;
1240}
1241static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
1242{
1243 return 0x000000f9;
1244}
1245static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
1246{
1247 return 0x000000fa;
1248}
1249static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
1250{
1251 return 0x000000fb;
1252}
1253static inline u32 gmmu_pte_kind_x8c24_v(void)
1254{
1255 return 0x000000fc;
1256}
1257static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
1258{
1259 return 0x000000fd;
1260}
1261static inline u32 gmmu_pte_kind_smsked_message_v(void)
1262{
1263 return 0x000000ca;
1264}
1265static inline u32 gmmu_pte_kind_smhost_message_v(void)
1266{
1267 return 0x000000cb;
1268}
1269static inline u32 gmmu_pte_kind_s8_v(void)
1270{
1271 return 0x0000002a;
1272}
1273static inline u32 gmmu_pte_kind_s8_2s_v(void)
1274{
1275 return 0x0000002b;
1276}
1277#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
new file mode 100644
index 00000000..9e3137e7
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -0,0 +1,4241 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gr_gp10b_h_
51#define _hw_gr_gp10b_h_
52
53static inline u32 gr_intr_r(void)
54{
55 return 0x00400100;
56}
57static inline u32 gr_intr_notify_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 gr_intr_notify_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 gr_intr_semaphore_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 gr_intr_semaphore_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 gr_intr_illegal_method_pending_f(void)
74{
75 return 0x10;
76}
77static inline u32 gr_intr_illegal_method_reset_f(void)
78{
79 return 0x10;
80}
81static inline u32 gr_intr_illegal_notify_pending_f(void)
82{
83 return 0x40;
84}
85static inline u32 gr_intr_illegal_notify_reset_f(void)
86{
87 return 0x40;
88}
89static inline u32 gr_intr_firmware_method_f(u32 v)
90{
91 return (v & 0x1) << 8;
92}
93static inline u32 gr_intr_firmware_method_pending_f(void)
94{
95 return 0x100;
96}
97static inline u32 gr_intr_firmware_method_reset_f(void)
98{
99 return 0x100;
100}
101static inline u32 gr_intr_illegal_class_pending_f(void)
102{
103 return 0x20;
104}
105static inline u32 gr_intr_illegal_class_reset_f(void)
106{
107 return 0x20;
108}
109static inline u32 gr_intr_fecs_error_pending_f(void)
110{
111 return 0x80000;
112}
113static inline u32 gr_intr_fecs_error_reset_f(void)
114{
115 return 0x80000;
116}
117static inline u32 gr_intr_class_error_pending_f(void)
118{
119 return 0x100000;
120}
121static inline u32 gr_intr_class_error_reset_f(void)
122{
123 return 0x100000;
124}
125static inline u32 gr_intr_exception_pending_f(void)
126{
127 return 0x200000;
128}
129static inline u32 gr_intr_exception_reset_f(void)
130{
131 return 0x200000;
132}
133static inline u32 gr_fecs_intr_r(void)
134{
135 return 0x00400144;
136}
137static inline u32 gr_class_error_r(void)
138{
139 return 0x00400110;
140}
141static inline u32 gr_class_error_code_v(u32 r)
142{
143 return (r >> 0) & 0xffff;
144}
145static inline u32 gr_intr_nonstall_r(void)
146{
147 return 0x00400120;
148}
149static inline u32 gr_intr_nonstall_trap_pending_f(void)
150{
151 return 0x2;
152}
153static inline u32 gr_intr_en_r(void)
154{
155 return 0x0040013c;
156}
157static inline u32 gr_exception_r(void)
158{
159 return 0x00400108;
160}
161static inline u32 gr_exception_fe_m(void)
162{
163 return 0x1 << 0;
164}
165static inline u32 gr_exception_gpc_m(void)
166{
167 return 0x1 << 24;
168}
169static inline u32 gr_exception_memfmt_m(void)
170{
171 return 0x1 << 1;
172}
173static inline u32 gr_exception_ds_m(void)
174{
175 return 0x1 << 4;
176}
177static inline u32 gr_exception1_r(void)
178{
179 return 0x00400118;
180}
181static inline u32 gr_exception1_gpc_0_pending_f(void)
182{
183 return 0x1;
184}
185static inline u32 gr_exception2_r(void)
186{
187 return 0x0040011c;
188}
189static inline u32 gr_exception_en_r(void)
190{
191 return 0x00400138;
192}
193static inline u32 gr_exception_en_fe_m(void)
194{
195 return 0x1 << 0;
196}
197static inline u32 gr_exception1_en_r(void)
198{
199 return 0x00400130;
200}
201static inline u32 gr_exception2_en_r(void)
202{
203 return 0x00400134;
204}
205static inline u32 gr_gpfifo_ctl_r(void)
206{
207 return 0x00400500;
208}
209static inline u32 gr_gpfifo_ctl_access_f(u32 v)
210{
211 return (v & 0x1) << 0;
212}
213static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
214{
215 return 0x0;
216}
217static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
218{
219 return 0x1;
220}
221static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
222{
223 return (v & 0x1) << 16;
224}
225static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
226{
227 return 0x00000001;
228}
229static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
230{
231 return 0x10000;
232}
233static inline u32 gr_gpfifo_status_r(void)
234{
235 return 0x00400504;
236}
237static inline u32 gr_trapped_addr_r(void)
238{
239 return 0x00400704;
240}
241static inline u32 gr_trapped_addr_mthd_v(u32 r)
242{
243 return (r >> 2) & 0xfff;
244}
245static inline u32 gr_trapped_addr_subch_v(u32 r)
246{
247 return (r >> 16) & 0x7;
248}
249static inline u32 gr_trapped_data_lo_r(void)
250{
251 return 0x00400708;
252}
253static inline u32 gr_trapped_data_hi_r(void)
254{
255 return 0x0040070c;
256}
257static inline u32 gr_status_r(void)
258{
259 return 0x00400700;
260}
261static inline u32 gr_status_fe_method_upper_v(u32 r)
262{
263 return (r >> 1) & 0x1;
264}
265static inline u32 gr_status_fe_method_lower_v(u32 r)
266{
267 return (r >> 2) & 0x1;
268}
269static inline u32 gr_status_fe_method_lower_idle_v(void)
270{
271 return 0x00000000;
272}
273static inline u32 gr_status_fe_gi_v(u32 r)
274{
275 return (r >> 21) & 0x1;
276}
277static inline u32 gr_status_mask_r(void)
278{
279 return 0x00400610;
280}
281static inline u32 gr_status_1_r(void)
282{
283 return 0x00400604;
284}
285static inline u32 gr_status_2_r(void)
286{
287 return 0x00400608;
288}
289static inline u32 gr_engine_status_r(void)
290{
291 return 0x0040060c;
292}
293static inline u32 gr_engine_status_value_busy_f(void)
294{
295 return 0x1;
296}
297static inline u32 gr_pri_be0_becs_be_exception_r(void)
298{
299 return 0x00410204;
300}
301static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
302{
303 return 0x00410208;
304}
305static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
306{
307 return 0x00502c90;
308}
309static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
310{
311 return 0x00502c94;
312}
313static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
314{
315 return 0x00504508;
316}
317static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
318{
319 return 0x0050450c;
320}
321static inline u32 gr_activity_0_r(void)
322{
323 return 0x00400380;
324}
325static inline u32 gr_activity_1_r(void)
326{
327 return 0x00400384;
328}
329static inline u32 gr_activity_2_r(void)
330{
331 return 0x00400388;
332}
333static inline u32 gr_activity_4_r(void)
334{
335 return 0x00400390;
336}
337static inline u32 gr_activity_4_gpc0_s(void)
338{
339 return 3;
340}
341static inline u32 gr_activity_4_gpc0_f(u32 v)
342{
343 return (v & 0x7) << 0;
344}
345static inline u32 gr_activity_4_gpc0_m(void)
346{
347 return 0x7 << 0;
348}
349static inline u32 gr_activity_4_gpc0_v(u32 r)
350{
351 return (r >> 0) & 0x7;
352}
353static inline u32 gr_activity_4_gpc0_empty_v(void)
354{
355 return 0x00000000;
356}
357static inline u32 gr_activity_4_gpc0_preempted_v(void)
358{
359 return 0x00000004;
360}
361static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
362{
363 return 0x00501000;
364}
365static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
366{
367 return 0x00419000;
368}
369static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
370{
371 return 0x1 << 1;
372}
373static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
374{
375 return 0x005046a4;
376}
377static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
378{
379 return 0x00419ea4;
380}
381static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
382{
383 return 0x1 << 0;
384}
385static inline u32 gr_pri_sked_activity_r(void)
386{
387 return 0x00407054;
388}
389static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
390{
391 return 0x00502c80;
392}
393static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
394{
395 return 0x00502c84;
396}
397static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
398{
399 return 0x00502c88;
400}
401static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
402{
403 return 0x00502c8c;
404}
405static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
406{
407 return 0x00504500;
408}
409static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
410{
411 return 0x00504d00;
412}
413static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
414{
415 return 0x00501d00;
416}
417static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
418{
419 return 0x0041ac80;
420}
421static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
422{
423 return 0x0041ac84;
424}
425static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
426{
427 return 0x0041ac88;
428}
429static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
430{
431 return 0x0041ac8c;
432}
433static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
434{
435 return 0x0041c500;
436}
437static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
438{
439 return 0x0041cd00;
440}
441static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
442{
443 return 0x00419d00;
444}
445static inline u32 gr_pri_be0_becs_be_activity0_r(void)
446{
447 return 0x00410200;
448}
449static inline u32 gr_pri_be1_becs_be_activity0_r(void)
450{
451 return 0x00410600;
452}
453static inline u32 gr_pri_bes_becs_be_activity0_r(void)
454{
455 return 0x00408a00;
456}
457static inline u32 gr_pri_ds_mpipe_status_r(void)
458{
459 return 0x00405858;
460}
461static inline u32 gr_pri_fe_go_idle_info_r(void)
462{
463 return 0x00404194;
464}
465static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
466{
467 return 0x00504238;
468}
469static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
470{
471 return 0x005046b8;
472}
473static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_b(void)
474{
475 return 4;
476}
477static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
478{
479 return 0x10;
480}
481static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
482{
483 return 0x20;
484}
485static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
486{
487 return 0x40;
488}
489static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
490{
491 return 0x80;
492}
493static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_b(void)
494{
495 return 8;
496}
497static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
498{
499 return 0x100;
500}
501static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
502{
503 return 0x200;
504}
505static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
506{
507 return 0x400;
508}
509static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
510{
511 return 0x800;
512}
513static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
514{
515 return 0x005044a0;
516}
517static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
518{
519 return 0x1;
520}
521static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
522{
523 return 0x2;
524}
525static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
526{
527 return 0x10;
528}
529static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
530{
531 return 0x20;
532}
533static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
534{
535 return 0x100;
536}
537static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
538{
539 return 0x200;
540}
541static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
542{
543 return 0x005046bc;
544}
545static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
546{
547 return 0x005046c0;
548}
549static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
550{
551 return 0x005044a4;
552}
553static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
554{
555 return 0xff << 0;
556}
557static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
558{
559 return (r >> 0) & 0xff;
560}
561static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
562{
563 return 0xff << 8;
564}
565static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
566{
567 return (r >> 8) & 0xff;
568}
569static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
570{
571 return 0xff << 16;
572}
573static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
574{
575 return (r >> 16) & 0xff;
576}
577static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
578{
579 return 0x005042c4;
580}
581static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
582{
583 return 0x0;
584}
585static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
586{
587 return 0x1;
588}
589static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
590{
591 return 0x2;
592}
593static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void)
594{
595 return 0x00504218;
596}
597static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void)
598{
599 return 0xffff << 0;
600}
601static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r)
602{
603 return (r >> 0) & 0xffff;
604}
605static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void)
606{
607 return 0xffff << 16;
608}
609static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r)
610{
611 return (r >> 16) & 0xffff;
612}
613static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void)
614{
615 return 0x005042ec;
616}
617static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void)
618{
619 return 0xffff << 0;
620}
621static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r)
622{
623 return (r >> 0) & 0xffff;
624}
625static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void)
626{
627 return 0xffff << 16;
628}
629static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r)
630{
631 return (r >> 16) & 0xffff;
632}
633static inline u32 gr_pri_be0_crop_status1_r(void)
634{
635 return 0x00410134;
636}
637static inline u32 gr_pri_bes_crop_status1_r(void)
638{
639 return 0x00408934;
640}
641static inline u32 gr_pri_be0_zrop_status_r(void)
642{
643 return 0x00410048;
644}
645static inline u32 gr_pri_be0_zrop_status2_r(void)
646{
647 return 0x0041004c;
648}
649static inline u32 gr_pri_bes_zrop_status_r(void)
650{
651 return 0x00408848;
652}
653static inline u32 gr_pri_bes_zrop_status2_r(void)
654{
655 return 0x0040884c;
656}
657static inline u32 gr_pipe_bundle_address_r(void)
658{
659 return 0x00400200;
660}
661static inline u32 gr_pipe_bundle_address_value_v(u32 r)
662{
663 return (r >> 0) & 0xffff;
664}
665static inline u32 gr_pipe_bundle_data_r(void)
666{
667 return 0x00400204;
668}
669static inline u32 gr_pipe_bundle_config_r(void)
670{
671 return 0x00400208;
672}
673static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
674{
675 return 0x0;
676}
677static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
678{
679 return 0x80000000;
680}
681static inline u32 gr_fe_hww_esr_r(void)
682{
683 return 0x00404000;
684}
685static inline u32 gr_fe_hww_esr_reset_active_f(void)
686{
687 return 0x40000000;
688}
689static inline u32 gr_fe_hww_esr_en_enable_f(void)
690{
691 return 0x80000000;
692}
693static inline u32 gr_fe_go_idle_timeout_r(void)
694{
695 return 0x00404154;
696}
697static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
698{
699 return (v & 0xffffffff) << 0;
700}
701static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
702{
703 return 0x0;
704}
705static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
706{
707 return 0x7fffffff;
708}
709static inline u32 gr_fe_object_table_r(u32 i)
710{
711 return 0x00404200 + i*4;
712}
713static inline u32 gr_fe_object_table_nvclass_v(u32 r)
714{
715 return (r >> 0) & 0xffff;
716}
717static inline u32 gr_fe_tpc_fs_r(void)
718{
719 return 0x004041c4;
720}
721static inline u32 gr_pri_mme_shadow_raw_index_r(void)
722{
723 return 0x00404488;
724}
725static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
726{
727 return 0x80000000;
728}
729static inline u32 gr_pri_mme_shadow_raw_data_r(void)
730{
731 return 0x0040448c;
732}
733static inline u32 gr_mme_hww_esr_r(void)
734{
735 return 0x00404490;
736}
737static inline u32 gr_mme_hww_esr_reset_active_f(void)
738{
739 return 0x40000000;
740}
741static inline u32 gr_mme_hww_esr_en_enable_f(void)
742{
743 return 0x80000000;
744}
745static inline u32 gr_memfmt_hww_esr_r(void)
746{
747 return 0x00404600;
748}
749static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
750{
751 return 0x40000000;
752}
753static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
754{
755 return 0x80000000;
756}
757static inline u32 gr_fecs_cpuctl_r(void)
758{
759 return 0x00409100;
760}
761static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
762{
763 return (v & 0x1) << 1;
764}
765static inline u32 gr_fecs_cpuctl_alias_r(void)
766{
767 return 0x00409130;
768}
769static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
770{
771 return (v & 0x1) << 1;
772}
773static inline u32 gr_fecs_dmactl_r(void)
774{
775 return 0x0040910c;
776}
777static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
778{
779 return (v & 0x1) << 0;
780}
781static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
782{
783 return 0x1 << 1;
784}
785static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
786{
787 return 0x1 << 2;
788}
789static inline u32 gr_fecs_os_r(void)
790{
791 return 0x00409080;
792}
793static inline u32 gr_fecs_idlestate_r(void)
794{
795 return 0x0040904c;
796}
797static inline u32 gr_fecs_mailbox0_r(void)
798{
799 return 0x00409040;
800}
801static inline u32 gr_fecs_mailbox1_r(void)
802{
803 return 0x00409044;
804}
805static inline u32 gr_fecs_irqstat_r(void)
806{
807 return 0x00409008;
808}
809static inline u32 gr_fecs_irqmode_r(void)
810{
811 return 0x0040900c;
812}
813static inline u32 gr_fecs_irqmask_r(void)
814{
815 return 0x00409018;
816}
817static inline u32 gr_fecs_irqdest_r(void)
818{
819 return 0x0040901c;
820}
821static inline u32 gr_fecs_curctx_r(void)
822{
823 return 0x00409050;
824}
825static inline u32 gr_fecs_nxtctx_r(void)
826{
827 return 0x00409054;
828}
829static inline u32 gr_fecs_engctl_r(void)
830{
831 return 0x004090a4;
832}
833static inline u32 gr_fecs_debug1_r(void)
834{
835 return 0x00409090;
836}
837static inline u32 gr_fecs_debuginfo_r(void)
838{
839 return 0x00409094;
840}
841static inline u32 gr_fecs_icd_cmd_r(void)
842{
843 return 0x00409200;
844}
845static inline u32 gr_fecs_icd_cmd_opc_s(void)
846{
847 return 4;
848}
849static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
850{
851 return (v & 0xf) << 0;
852}
853static inline u32 gr_fecs_icd_cmd_opc_m(void)
854{
855 return 0xf << 0;
856}
857static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
858{
859 return (r >> 0) & 0xf;
860}
861static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
862{
863 return 0x8;
864}
865static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
866{
867 return 0xe;
868}
869static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
870{
871 return (v & 0x1f) << 8;
872}
873static inline u32 gr_fecs_icd_rdata_r(void)
874{
875 return 0x0040920c;
876}
877static inline u32 gr_fecs_imemc_r(u32 i)
878{
879 return 0x00409180 + i*16;
880}
881static inline u32 gr_fecs_imemc_offs_f(u32 v)
882{
883 return (v & 0x3f) << 2;
884}
885static inline u32 gr_fecs_imemc_blk_f(u32 v)
886{
887 return (v & 0xff) << 8;
888}
889static inline u32 gr_fecs_imemc_aincw_f(u32 v)
890{
891 return (v & 0x1) << 24;
892}
893static inline u32 gr_fecs_imemd_r(u32 i)
894{
895 return 0x00409184 + i*16;
896}
897static inline u32 gr_fecs_imemt_r(u32 i)
898{
899 return 0x00409188 + i*16;
900}
901static inline u32 gr_fecs_imemt_tag_f(u32 v)
902{
903 return (v & 0xffff) << 0;
904}
905static inline u32 gr_fecs_dmemc_r(u32 i)
906{
907 return 0x004091c0 + i*8;
908}
909static inline u32 gr_fecs_dmemc_offs_s(void)
910{
911 return 6;
912}
913static inline u32 gr_fecs_dmemc_offs_f(u32 v)
914{
915 return (v & 0x3f) << 2;
916}
917static inline u32 gr_fecs_dmemc_offs_m(void)
918{
919 return 0x3f << 2;
920}
921static inline u32 gr_fecs_dmemc_offs_v(u32 r)
922{
923 return (r >> 2) & 0x3f;
924}
925static inline u32 gr_fecs_dmemc_blk_f(u32 v)
926{
927 return (v & 0xff) << 8;
928}
929static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
930{
931 return (v & 0x1) << 24;
932}
933static inline u32 gr_fecs_dmemd_r(u32 i)
934{
935 return 0x004091c4 + i*8;
936}
937static inline u32 gr_fecs_dmatrfbase_r(void)
938{
939 return 0x00409110;
940}
941static inline u32 gr_fecs_dmatrfmoffs_r(void)
942{
943 return 0x00409114;
944}
945static inline u32 gr_fecs_dmatrffboffs_r(void)
946{
947 return 0x0040911c;
948}
949static inline u32 gr_fecs_dmatrfcmd_r(void)
950{
951 return 0x00409118;
952}
953static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
954{
955 return (v & 0x1) << 4;
956}
957static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
958{
959 return (v & 0x1) << 5;
960}
961static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
962{
963 return (v & 0x7) << 8;
964}
965static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
966{
967 return (v & 0x7) << 12;
968}
969static inline u32 gr_fecs_bootvec_r(void)
970{
971 return 0x00409104;
972}
973static inline u32 gr_fecs_bootvec_vec_f(u32 v)
974{
975 return (v & 0xffffffff) << 0;
976}
977static inline u32 gr_fecs_falcon_hwcfg_r(void)
978{
979 return 0x00409108;
980}
981static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
982{
983 return 0x0041a108;
984}
985static inline u32 gr_fecs_falcon_rm_r(void)
986{
987 return 0x00409084;
988}
989static inline u32 gr_fecs_current_ctx_r(void)
990{
991 return 0x00409b00;
992}
993static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
994{
995 return (v & 0xfffffff) << 0;
996}
997static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
998{
999 return (r >> 0) & 0xfffffff;
1000}
1001static inline u32 gr_fecs_current_ctx_target_s(void)
1002{
1003 return 2;
1004}
1005static inline u32 gr_fecs_current_ctx_target_f(u32 v)
1006{
1007 return (v & 0x3) << 28;
1008}
1009static inline u32 gr_fecs_current_ctx_target_m(void)
1010{
1011 return 0x3 << 28;
1012}
1013static inline u32 gr_fecs_current_ctx_target_v(u32 r)
1014{
1015 return (r >> 28) & 0x3;
1016}
1017static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
1018{
1019 return 0x0;
1020}
1021static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
1022{
1023 return 0x20000000;
1024}
1025static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
1026{
1027 return 0x30000000;
1028}
1029static inline u32 gr_fecs_current_ctx_valid_s(void)
1030{
1031 return 1;
1032}
1033static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
1034{
1035 return (v & 0x1) << 31;
1036}
1037static inline u32 gr_fecs_current_ctx_valid_m(void)
1038{
1039 return 0x1 << 31;
1040}
1041static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
1042{
1043 return (r >> 31) & 0x1;
1044}
1045static inline u32 gr_fecs_current_ctx_valid_false_f(void)
1046{
1047 return 0x0;
1048}
1049static inline u32 gr_fecs_method_data_r(void)
1050{
1051 return 0x00409500;
1052}
1053static inline u32 gr_fecs_method_push_r(void)
1054{
1055 return 0x00409504;
1056}
1057static inline u32 gr_fecs_method_push_adr_f(u32 v)
1058{
1059 return (v & 0xfff) << 0;
1060}
1061static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
1062{
1063 return 0x00000003;
1064}
1065static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
1066{
1067 return 0x3;
1068}
1069static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
1070{
1071 return 0x00000010;
1072}
1073static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
1074{
1075 return 0x00000009;
1076}
1077static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
1078{
1079 return 0x00000015;
1080}
1081static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
1082{
1083 return 0x00000016;
1084}
1085static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
1086{
1087 return 0x00000025;
1088}
1089static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
1090{
1091 return 0x00000030;
1092}
1093static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
1094{
1095 return 0x00000031;
1096}
1097static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
1098{
1099 return 0x00000032;
1100}
1101static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
1102{
1103 return 0x00000038;
1104}
1105static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
1106{
1107 return 0x00000039;
1108}
1109static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
1110{
1111 return 0x21;
1112}
1113static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void)
1114{
1115 return 0x0000003d;
1116}
1117static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
1118{
1119 return 0x0000001a;
1120}
1121static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
1122{
1123 return 0x00000004;
1124}
1125static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void)
1126{
1127 return 0x0000003a;
1128}
1129static inline u32 gr_fecs_host_int_status_r(void)
1130{
1131 return 0x00409c18;
1132}
1133static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
1134{
1135 return (v & 0x1) << 16;
1136}
1137static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
1138{
1139 return (v & 0x1) << 17;
1140}
1141static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
1142{
1143 return (v & 0x1) << 18;
1144}
1145static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
1146{
1147 return (v & 0xffff) << 0;
1148}
1149static inline u32 gr_fecs_host_int_clear_r(void)
1150{
1151 return 0x00409c20;
1152}
1153static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
1154{
1155 return (v & 0x1) << 1;
1156}
1157static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
1158{
1159 return 0x2;
1160}
1161static inline u32 gr_fecs_host_int_enable_r(void)
1162{
1163 return 0x00409c24;
1164}
1165static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
1166{
1167 return 0x2;
1168}
1169static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
1170{
1171 return 0x10000;
1172}
1173static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
1174{
1175 return 0x20000;
1176}
1177static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
1178{
1179 return 0x40000;
1180}
1181static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
1182{
1183 return 0x80000;
1184}
1185static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
1186{
1187 return 0x00409614;
1188}
1189static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
1190{
1191 return 0x0;
1192}
1193static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
1194{
1195 return 0x0;
1196}
1197static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
1198{
1199 return 0x0;
1200}
1201static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
1202{
1203 return 0x10;
1204}
1205static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
1206{
1207 return 0x20;
1208}
1209static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1210{
1211 return 0x40;
1212}
1213static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1214{
1215 return 0x0;
1216}
1217static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1218{
1219 return 0x100;
1220}
1221static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1222{
1223 return 0x0;
1224}
1225static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1226{
1227 return 0x200;
1228}
1229static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1230{
1231 return 1;
1232}
1233static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1234{
1235 return (v & 0x1) << 10;
1236}
1237static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1238{
1239 return 0x1 << 10;
1240}
1241static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1242{
1243 return (r >> 10) & 0x1;
1244}
1245static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1246{
1247 return 0x0;
1248}
1249static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1250{
1251 return 0x400;
1252}
1253static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1254{
1255 return 0x0040960c;
1256}
1257static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1258{
1259 return 0x00409800 + i*4;
1260}
1261static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1262{
1263 return 0x00000010;
1264}
1265static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1266{
1267 return (v & 0xffffffff) << 0;
1268}
1269static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1270{
1271 return 0x00000001;
1272}
1273static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1274{
1275 return 0x00000002;
1276}
1277static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1278{
1279 return 0x004098c0 + i*4;
1280}
1281static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1282{
1283 return (v & 0xffffffff) << 0;
1284}
1285static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1286{
1287 return 0x00409840 + i*4;
1288}
1289static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1290{
1291 return (v & 0xffffffff) << 0;
1292}
1293static inline u32 gr_fecs_fs_r(void)
1294{
1295 return 0x00409604;
1296}
1297static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1298{
1299 return 5;
1300}
1301static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1302{
1303 return (v & 0x1f) << 0;
1304}
1305static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1306{
1307 return 0x1f << 0;
1308}
1309static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1310{
1311 return (r >> 0) & 0x1f;
1312}
1313static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1314{
1315 return 5;
1316}
1317static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1318{
1319 return (v & 0x1f) << 16;
1320}
1321static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1322{
1323 return 0x1f << 16;
1324}
1325static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1326{
1327 return (r >> 16) & 0x1f;
1328}
1329static inline u32 gr_fecs_cfg_r(void)
1330{
1331 return 0x00409620;
1332}
1333static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1334{
1335 return (r >> 0) & 0xff;
1336}
1337static inline u32 gr_fecs_rc_lanes_r(void)
1338{
1339 return 0x00409880;
1340}
1341static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1342{
1343 return 6;
1344}
1345static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1346{
1347 return (v & 0x3f) << 0;
1348}
1349static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1350{
1351 return 0x3f << 0;
1352}
1353static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1354{
1355 return (r >> 0) & 0x3f;
1356}
1357static inline u32 gr_fecs_ctxsw_status_1_r(void)
1358{
1359 return 0x00409400;
1360}
1361static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1362{
1363 return 1;
1364}
1365static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1366{
1367 return (v & 0x1) << 12;
1368}
1369static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1370{
1371 return 0x1 << 12;
1372}
1373static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1374{
1375 return (r >> 12) & 0x1;
1376}
1377static inline u32 gr_fecs_arb_ctx_adr_r(void)
1378{
1379 return 0x00409a24;
1380}
1381static inline u32 gr_fecs_new_ctx_r(void)
1382{
1383 return 0x00409b04;
1384}
1385static inline u32 gr_fecs_new_ctx_ptr_s(void)
1386{
1387 return 28;
1388}
1389static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1390{
1391 return (v & 0xfffffff) << 0;
1392}
1393static inline u32 gr_fecs_new_ctx_ptr_m(void)
1394{
1395 return 0xfffffff << 0;
1396}
1397static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1398{
1399 return (r >> 0) & 0xfffffff;
1400}
1401static inline u32 gr_fecs_new_ctx_target_s(void)
1402{
1403 return 2;
1404}
1405static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1406{
1407 return (v & 0x3) << 28;
1408}
1409static inline u32 gr_fecs_new_ctx_target_m(void)
1410{
1411 return 0x3 << 28;
1412}
1413static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1414{
1415 return (r >> 28) & 0x3;
1416}
1417static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
1418{
1419 return 0x0;
1420}
1421static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
1422{
1423 return 0x30000000;
1424}
1425static inline u32 gr_fecs_new_ctx_valid_s(void)
1426{
1427 return 1;
1428}
1429static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1430{
1431 return (v & 0x1) << 31;
1432}
1433static inline u32 gr_fecs_new_ctx_valid_m(void)
1434{
1435 return 0x1 << 31;
1436}
1437static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1438{
1439 return (r >> 31) & 0x1;
1440}
1441static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1442{
1443 return 0x00409a0c;
1444}
1445static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1446{
1447 return 28;
1448}
1449static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1450{
1451 return (v & 0xfffffff) << 0;
1452}
1453static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1454{
1455 return 0xfffffff << 0;
1456}
1457static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1458{
1459 return (r >> 0) & 0xfffffff;
1460}
1461static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1462{
1463 return 2;
1464}
1465static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1466{
1467 return (v & 0x3) << 28;
1468}
1469static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1470{
1471 return 0x3 << 28;
1472}
1473static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1474{
1475 return (r >> 28) & 0x3;
1476}
1477static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
1478{
1479 return 0x0;
1480}
1481static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
1482{
1483 return 0x30000000;
1484}
1485static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1486{
1487 return 0x00409a10;
1488}
1489static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1490{
1491 return 5;
1492}
1493static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1494{
1495 return (v & 0x1f) << 0;
1496}
1497static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1498{
1499 return 0x1f << 0;
1500}
1501static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1502{
1503 return (r >> 0) & 0x1f;
1504}
1505static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1506{
1507 return 0x00409c00;
1508}
1509static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1510{
1511 return 0x00502c04;
1512}
1513static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1514{
1515 return 0x00502400;
1516}
1517static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1518{
1519 return 0x00409420;
1520}
1521static inline u32 gr_fecs_feature_override_ecc_r(void)
1522{
1523 return 0x00409658;
1524}
1525static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
1526{
1527 return (r >> 3) & 0x1;
1528}
1529static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r)
1530{
1531 return (r >> 7) & 0x1;
1532}
1533static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r)
1534{
1535 return (r >> 11) & 0x1;
1536}
1537static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
1538{
1539 return (r >> 15) & 0x1;
1540}
1541static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
1542{
1543 return (r >> 0) & 0x1;
1544}
1545static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r)
1546{
1547 return (r >> 4) & 0x1;
1548}
1549static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r)
1550{
1551 return (r >> 8) & 0x1;
1552}
1553static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
1554{
1555 return (r >> 12) & 0x1;
1556}
1557static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1558{
1559 return 0x00502420;
1560}
1561static inline u32 gr_rstr2d_gpc_map0_r(void)
1562{
1563 return 0x0040780c;
1564}
1565static inline u32 gr_rstr2d_gpc_map1_r(void)
1566{
1567 return 0x00407810;
1568}
1569static inline u32 gr_rstr2d_gpc_map2_r(void)
1570{
1571 return 0x00407814;
1572}
1573static inline u32 gr_rstr2d_gpc_map3_r(void)
1574{
1575 return 0x00407818;
1576}
1577static inline u32 gr_rstr2d_gpc_map4_r(void)
1578{
1579 return 0x0040781c;
1580}
1581static inline u32 gr_rstr2d_gpc_map5_r(void)
1582{
1583 return 0x00407820;
1584}
1585static inline u32 gr_rstr2d_map_table_cfg_r(void)
1586{
1587 return 0x004078bc;
1588}
1589static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1590{
1591 return (v & 0xff) << 0;
1592}
1593static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1594{
1595 return (v & 0xff) << 8;
1596}
1597static inline u32 gr_pd_hww_esr_r(void)
1598{
1599 return 0x00406018;
1600}
1601static inline u32 gr_pd_hww_esr_reset_active_f(void)
1602{
1603 return 0x40000000;
1604}
1605static inline u32 gr_pd_hww_esr_en_enable_f(void)
1606{
1607 return 0x80000000;
1608}
1609static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1610{
1611 return 0x00406028 + i*4;
1612}
1613static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1614{
1615 return 0x00000004;
1616}
1617static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1618{
1619 return (v & 0xf) << 0;
1620}
1621static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1622{
1623 return (v & 0xf) << 4;
1624}
1625static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1626{
1627 return (v & 0xf) << 8;
1628}
1629static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1630{
1631 return (v & 0xf) << 12;
1632}
1633static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1634{
1635 return (v & 0xf) << 16;
1636}
1637static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1638{
1639 return (v & 0xf) << 20;
1640}
1641static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1642{
1643 return (v & 0xf) << 24;
1644}
1645static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1646{
1647 return (v & 0xf) << 28;
1648}
1649static inline u32 gr_pd_ab_dist_cfg0_r(void)
1650{
1651 return 0x004064c0;
1652}
1653static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1654{
1655 return 0x80000000;
1656}
1657static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1658{
1659 return 0x0;
1660}
1661static inline u32 gr_pd_ab_dist_cfg1_r(void)
1662{
1663 return 0x004064c4;
1664}
1665static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
1666{
1667 return 0xffff;
1668}
1669static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
1670{
1671 return (v & 0xffff) << 16;
1672}
1673static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
1674{
1675 return 0x00000080;
1676}
1677static inline u32 gr_pd_ab_dist_cfg2_r(void)
1678{
1679 return 0x004064c8;
1680}
1681static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
1682{
1683 return (v & 0x1fff) << 0;
1684}
1685static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
1686{
1687 return 0x000001c0;
1688}
1689static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
1690{
1691 return (v & 0x1fff) << 16;
1692}
1693static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
1694{
1695 return 0x00000020;
1696}
1697static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
1698{
1699 return 0x00000182;
1700}
1701static inline u32 gr_pd_dist_skip_table_r(u32 i)
1702{
1703 return 0x004064d0 + i*4;
1704}
1705static inline u32 gr_pd_dist_skip_table__size_1_v(void)
1706{
1707 return 0x00000008;
1708}
1709static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
1710{
1711 return (v & 0xff) << 0;
1712}
1713static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
1714{
1715 return (v & 0xff) << 8;
1716}
1717static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
1718{
1719 return (v & 0xff) << 16;
1720}
1721static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
1722{
1723 return (v & 0xff) << 24;
1724}
1725static inline u32 gr_ds_debug_r(void)
1726{
1727 return 0x00405800;
1728}
1729static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
1730{
1731 return 0x0;
1732}
1733static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
1734{
1735 return 0x8000000;
1736}
1737static inline u32 gr_ds_zbc_color_r_r(void)
1738{
1739 return 0x00405804;
1740}
1741static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
1742{
1743 return (v & 0xffffffff) << 0;
1744}
1745static inline u32 gr_ds_zbc_color_g_r(void)
1746{
1747 return 0x00405808;
1748}
1749static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
1750{
1751 return (v & 0xffffffff) << 0;
1752}
1753static inline u32 gr_ds_zbc_color_b_r(void)
1754{
1755 return 0x0040580c;
1756}
1757static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
1758{
1759 return (v & 0xffffffff) << 0;
1760}
1761static inline u32 gr_ds_zbc_color_a_r(void)
1762{
1763 return 0x00405810;
1764}
1765static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
1766{
1767 return (v & 0xffffffff) << 0;
1768}
1769static inline u32 gr_ds_zbc_color_fmt_r(void)
1770{
1771 return 0x00405814;
1772}
1773static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
1774{
1775 return (v & 0x7f) << 0;
1776}
1777static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
1778{
1779 return 0x0;
1780}
1781static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
1782{
1783 return 0x00000001;
1784}
1785static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
1786{
1787 return 0x00000002;
1788}
1789static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
1790{
1791 return 0x00000004;
1792}
1793static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
1794{
1795 return 0x00000028;
1796}
1797static inline u32 gr_ds_zbc_z_r(void)
1798{
1799 return 0x00405818;
1800}
1801static inline u32 gr_ds_zbc_z_val_s(void)
1802{
1803 return 32;
1804}
1805static inline u32 gr_ds_zbc_z_val_f(u32 v)
1806{
1807 return (v & 0xffffffff) << 0;
1808}
1809static inline u32 gr_ds_zbc_z_val_m(void)
1810{
1811 return 0xffffffff << 0;
1812}
1813static inline u32 gr_ds_zbc_z_val_v(u32 r)
1814{
1815 return (r >> 0) & 0xffffffff;
1816}
1817static inline u32 gr_ds_zbc_z_val__init_v(void)
1818{
1819 return 0x00000000;
1820}
1821static inline u32 gr_ds_zbc_z_val__init_f(void)
1822{
1823 return 0x0;
1824}
1825static inline u32 gr_ds_zbc_z_fmt_r(void)
1826{
1827 return 0x0040581c;
1828}
1829static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
1830{
1831 return (v & 0x1) << 0;
1832}
1833static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
1834{
1835 return 0x0;
1836}
1837static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
1838{
1839 return 0x00000001;
1840}
1841static inline u32 gr_ds_zbc_tbl_index_r(void)
1842{
1843 return 0x00405820;
1844}
1845static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
1846{
1847 return (v & 0xf) << 0;
1848}
1849static inline u32 gr_ds_zbc_tbl_ld_r(void)
1850{
1851 return 0x00405824;
1852}
1853static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
1854{
1855 return 0x0;
1856}
1857static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
1858{
1859 return 0x1;
1860}
1861static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
1862{
1863 return 0x0;
1864}
1865static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
1866{
1867 return 0x4;
1868}
1869static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
1870{
1871 return 0x00405830;
1872}
1873static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
1874{
1875 return (v & 0x3fffff) << 0;
1876}
1877static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
1878{
1879 return 0x0040585c;
1880}
1881static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
1882{
1883 return (v & 0xffff) << 0;
1884}
1885static inline u32 gr_ds_hww_esr_r(void)
1886{
1887 return 0x00405840;
1888}
1889static inline u32 gr_ds_hww_esr_reset_s(void)
1890{
1891 return 1;
1892}
1893static inline u32 gr_ds_hww_esr_reset_f(u32 v)
1894{
1895 return (v & 0x1) << 30;
1896}
1897static inline u32 gr_ds_hww_esr_reset_m(void)
1898{
1899 return 0x1 << 30;
1900}
1901static inline u32 gr_ds_hww_esr_reset_v(u32 r)
1902{
1903 return (r >> 30) & 0x1;
1904}
1905static inline u32 gr_ds_hww_esr_reset_task_v(void)
1906{
1907 return 0x00000001;
1908}
1909static inline u32 gr_ds_hww_esr_reset_task_f(void)
1910{
1911 return 0x40000000;
1912}
1913static inline u32 gr_ds_hww_esr_en_enabled_f(void)
1914{
1915 return 0x80000000;
1916}
1917static inline u32 gr_ds_hww_esr_2_r(void)
1918{
1919 return 0x00405848;
1920}
1921static inline u32 gr_ds_hww_esr_2_reset_s(void)
1922{
1923 return 1;
1924}
1925static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
1926{
1927 return (v & 0x1) << 30;
1928}
1929static inline u32 gr_ds_hww_esr_2_reset_m(void)
1930{
1931 return 0x1 << 30;
1932}
1933static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
1934{
1935 return (r >> 30) & 0x1;
1936}
1937static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
1938{
1939 return 0x00000001;
1940}
1941static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
1942{
1943 return 0x40000000;
1944}
1945static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
1946{
1947 return 0x80000000;
1948}
1949static inline u32 gr_ds_hww_report_mask_r(void)
1950{
1951 return 0x00405844;
1952}
1953static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
1954{
1955 return 0x1;
1956}
1957static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
1958{
1959 return 0x2;
1960}
1961static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
1962{
1963 return 0x4;
1964}
1965static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
1966{
1967 return 0x8;
1968}
1969static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
1970{
1971 return 0x10;
1972}
1973static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
1974{
1975 return 0x20;
1976}
1977static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
1978{
1979 return 0x40;
1980}
1981static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
1982{
1983 return 0x80;
1984}
1985static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
1986{
1987 return 0x100;
1988}
1989static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
1990{
1991 return 0x200;
1992}
1993static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
1994{
1995 return 0x400;
1996}
1997static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
1998{
1999 return 0x800;
2000}
2001static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
2002{
2003 return 0x1000;
2004}
2005static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
2006{
2007 return 0x2000;
2008}
2009static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
2010{
2011 return 0x4000;
2012}
2013static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
2014{
2015 return 0x8000;
2016}
2017static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
2018{
2019 return 0x10000;
2020}
2021static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
2022{
2023 return 0x20000;
2024}
2025static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
2026{
2027 return 0x40000;
2028}
2029static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
2030{
2031 return 0x80000;
2032}
2033static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
2034{
2035 return 0x100000;
2036}
2037static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
2038{
2039 return 0x200000;
2040}
2041static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
2042{
2043 return 0x400000;
2044}
2045static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
2046{
2047 return 0x800000;
2048}
2049static inline u32 gr_ds_hww_report_mask_2_r(void)
2050{
2051 return 0x0040584c;
2052}
2053static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
2054{
2055 return 0x1;
2056}
2057static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
2058{
2059 return 0x00405870 + i*4;
2060}
2061static inline u32 gr_scc_bundle_cb_base_r(void)
2062{
2063 return 0x00408004;
2064}
2065static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
2066{
2067 return (v & 0xffffffff) << 0;
2068}
2069static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
2070{
2071 return 0x00000008;
2072}
2073static inline u32 gr_scc_bundle_cb_size_r(void)
2074{
2075 return 0x00408008;
2076}
2077static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
2078{
2079 return (v & 0x7ff) << 0;
2080}
2081static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
2082{
2083 return 0x00000018;
2084}
2085static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
2086{
2087 return 0x00000100;
2088}
2089static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
2090{
2091 return 0x00000000;
2092}
2093static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
2094{
2095 return 0x0;
2096}
2097static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
2098{
2099 return 0x80000000;
2100}
2101static inline u32 gr_scc_pagepool_base_r(void)
2102{
2103 return 0x0040800c;
2104}
2105static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
2106{
2107 return (v & 0xffffffff) << 0;
2108}
2109static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
2110{
2111 return 0x00000008;
2112}
2113static inline u32 gr_scc_pagepool_r(void)
2114{
2115 return 0x00408010;
2116}
2117static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
2118{
2119 return (v & 0x3ff) << 0;
2120}
2121static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
2122{
2123 return 0x00000000;
2124}
2125static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
2126{
2127 return 0x00000200;
2128}
2129static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
2130{
2131 return 0x00000100;
2132}
2133static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
2134{
2135 return 10;
2136}
2137static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
2138{
2139 return (v & 0x3ff) << 10;
2140}
2141static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
2142{
2143 return 0x3ff << 10;
2144}
2145static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
2146{
2147 return (r >> 10) & 0x3ff;
2148}
2149static inline u32 gr_scc_pagepool_valid_true_f(void)
2150{
2151 return 0x80000000;
2152}
2153static inline u32 gr_scc_init_r(void)
2154{
2155 return 0x0040802c;
2156}
2157static inline u32 gr_scc_init_ram_trigger_f(void)
2158{
2159 return 0x1;
2160}
2161static inline u32 gr_scc_hww_esr_r(void)
2162{
2163 return 0x00408030;
2164}
2165static inline u32 gr_scc_hww_esr_reset_active_f(void)
2166{
2167 return 0x40000000;
2168}
2169static inline u32 gr_scc_hww_esr_en_enable_f(void)
2170{
2171 return 0x80000000;
2172}
2173static inline u32 gr_sked_hww_esr_r(void)
2174{
2175 return 0x00407020;
2176}
2177static inline u32 gr_sked_hww_esr_reset_active_f(void)
2178{
2179 return 0x40000000;
2180}
2181static inline u32 gr_cwd_fs_r(void)
2182{
2183 return 0x00405b00;
2184}
2185static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
2186{
2187 return (v & 0xff) << 0;
2188}
2189static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
2190{
2191 return (v & 0xff) << 8;
2192}
2193static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
2194{
2195 return 0x00405b60 + i*4;
2196}
2197static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
2198{
2199 return 4;
2200}
2201static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
2202{
2203 return (v & 0xf) << 0;
2204}
2205static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
2206{
2207 return 4;
2208}
2209static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
2210{
2211 return (v & 0xf) << 4;
2212}
2213static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
2214{
2215 return (v & 0xf) << 8;
2216}
2217static inline u32 gr_cwd_sm_id_r(u32 i)
2218{
2219 return 0x00405ba0 + i*4;
2220}
2221static inline u32 gr_cwd_sm_id__size_1_v(void)
2222{
2223 return 0x00000010;
2224}
2225static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
2226{
2227 return (v & 0xff) << 0;
2228}
2229static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
2230{
2231 return (v & 0xff) << 8;
2232}
2233static inline u32 gr_gpc0_fs_gpc_r(void)
2234{
2235 return 0x00502608;
2236}
2237static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
2238{
2239 return (r >> 0) & 0x1f;
2240}
2241static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
2242{
2243 return (r >> 16) & 0x1f;
2244}
2245static inline u32 gr_gpc0_cfg_r(void)
2246{
2247 return 0x00502620;
2248}
2249static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
2250{
2251 return (r >> 0) & 0xff;
2252}
2253static inline u32 gr_gpccs_rc_lanes_r(void)
2254{
2255 return 0x00502880;
2256}
2257static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
2258{
2259 return 6;
2260}
2261static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
2262{
2263 return (v & 0x3f) << 0;
2264}
2265static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
2266{
2267 return 0x3f << 0;
2268}
2269static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2270{
2271 return (r >> 0) & 0x3f;
2272}
2273static inline u32 gr_gpccs_rc_lane_size_r(void)
2274{
2275 return 0x00502910;
2276}
2277static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2278{
2279 return 24;
2280}
2281static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2282{
2283 return (v & 0xffffff) << 0;
2284}
2285static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2286{
2287 return 0xffffff << 0;
2288}
2289static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2290{
2291 return (r >> 0) & 0xffffff;
2292}
2293static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2294{
2295 return 0x00000000;
2296}
2297static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2298{
2299 return 0x0;
2300}
2301static inline u32 gr_gpc0_zcull_fs_r(void)
2302{
2303 return 0x00500910;
2304}
2305static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2306{
2307 return (v & 0x1ff) << 0;
2308}
2309static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2310{
2311 return (v & 0xf) << 16;
2312}
2313static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2314{
2315 return 0x00500914;
2316}
2317static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2318{
2319 return (v & 0xf) << 0;
2320}
2321static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2322{
2323 return (v & 0xf) << 8;
2324}
2325static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2326{
2327 return 0x00500918;
2328}
2329static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2330{
2331 return (v & 0xffffff) << 0;
2332}
2333static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2334{
2335 return 0x00800000;
2336}
2337static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2338{
2339 return 0x00500920;
2340}
2341static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2342{
2343 return (v & 0xffff) << 0;
2344}
2345static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2346{
2347 return 0x00500a04 + i*32;
2348}
2349static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2350{
2351 return 0x00000040;
2352}
2353static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2354{
2355 return 0x00000010;
2356}
2357static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2358{
2359 return 0x00500c10 + i*4;
2360}
2361static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2362{
2363 return (v & 0xff) << 0;
2364}
2365static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2366{
2367 return 0x00500c30 + i*4;
2368}
2369static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2370{
2371 return (r >> 0) & 0xff;
2372}
2373static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2374{
2375 return 0x00504088;
2376}
2377static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2378{
2379 return (v & 0xffff) << 0;
2380}
2381static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2382{
2383 return 0x00504698;
2384}
2385static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
2386{
2387 return (v & 0xffff) << 0;
2388}
2389static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
2390{
2391 return (r >> 0) & 0xffff;
2392}
2393static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2394{
2395 return 0x0050469c;
2396}
2397static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2398{
2399 return (r >> 0) & 0xff;
2400}
2401static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2402{
2403 return (r >> 8) & 0xfff;
2404}
2405static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
2406{
2407 return (r >> 20) & 0xfff;
2408}
2409static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2410{
2411 return 0x00503018;
2412}
2413static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2414{
2415 return 0x1 << 0;
2416}
2417static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2418{
2419 return 0x1;
2420}
2421static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
2422{
2423 return 0x005030c0;
2424}
2425static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
2426{
2427 return (v & 0x3fffff) << 0;
2428}
2429static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
2430{
2431 return 0x3fffff << 0;
2432}
2433static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
2434{
2435 return 0x00030000;
2436}
2437static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
2438{
2439 return 0x00030a00;
2440}
2441static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
2442{
2443 return 0x00000020;
2444}
2445static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
2446{
2447 return 0x005030f4;
2448}
2449static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
2450{
2451 return 0x005030e4;
2452}
2453static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
2454{
2455 return (v & 0xffff) << 0;
2456}
2457static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
2458{
2459 return 0xffff << 0;
2460}
2461static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
2462{
2463 return 0x00000800;
2464}
2465static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
2466{
2467 return 0x00000020;
2468}
2469static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
2470{
2471 return 0x005030f8;
2472}
2473static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
2474{
2475 return 0x005030f0;
2476}
2477static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
2478{
2479 return (v & 0x3fffff) << 0;
2480}
2481static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
2482{
2483 return 0x00030000;
2484}
2485static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
2486{
2487 return 0x00419b00;
2488}
2489static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
2490{
2491 return (v & 0xffffffff) << 0;
2492}
2493static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
2494{
2495 return 0x00419b04;
2496}
2497static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
2498{
2499 return 21;
2500}
2501static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
2502{
2503 return (v & 0x1fffff) << 0;
2504}
2505static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
2506{
2507 return 0x1fffff << 0;
2508}
2509static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
2510{
2511 return (r >> 0) & 0x1fffff;
2512}
2513static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
2514{
2515 return 0x80;
2516}
2517static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
2518{
2519 return 1;
2520}
2521static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
2522{
2523 return (v & 0x1) << 31;
2524}
2525static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
2526{
2527 return 0x1 << 31;
2528}
2529static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
2530{
2531 return (r >> 31) & 0x1;
2532}
2533static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
2534{
2535 return 0x80000000;
2536}
2537static inline u32 gr_gpccs_falcon_addr_r(void)
2538{
2539 return 0x0041a0ac;
2540}
2541static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2542{
2543 return 6;
2544}
2545static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2546{
2547 return (v & 0x3f) << 0;
2548}
2549static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2550{
2551 return 0x3f << 0;
2552}
2553static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2554{
2555 return (r >> 0) & 0x3f;
2556}
2557static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2558{
2559 return 0x00000000;
2560}
2561static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2562{
2563 return 0x0;
2564}
2565static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2566{
2567 return 6;
2568}
2569static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2570{
2571 return (v & 0x3f) << 6;
2572}
2573static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2574{
2575 return 0x3f << 6;
2576}
2577static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2578{
2579 return (r >> 6) & 0x3f;
2580}
2581static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2582{
2583 return 0x00000000;
2584}
2585static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2586{
2587 return 0x0;
2588}
2589static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2590{
2591 return 12;
2592}
2593static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2594{
2595 return (v & 0xfff) << 0;
2596}
2597static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2598{
2599 return 0xfff << 0;
2600}
2601static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2602{
2603 return (r >> 0) & 0xfff;
2604}
2605static inline u32 gr_gpccs_cpuctl_r(void)
2606{
2607 return 0x0041a100;
2608}
2609static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2610{
2611 return (v & 0x1) << 1;
2612}
2613static inline u32 gr_gpccs_dmactl_r(void)
2614{
2615 return 0x0041a10c;
2616}
2617static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2618{
2619 return (v & 0x1) << 0;
2620}
2621static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2622{
2623 return 0x1 << 1;
2624}
2625static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2626{
2627 return 0x1 << 2;
2628}
2629static inline u32 gr_gpccs_imemc_r(u32 i)
2630{
2631 return 0x0041a180 + i*16;
2632}
2633static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2634{
2635 return (v & 0x3f) << 2;
2636}
2637static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2638{
2639 return (v & 0xff) << 8;
2640}
2641static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2642{
2643 return (v & 0x1) << 24;
2644}
2645static inline u32 gr_gpccs_imemd_r(u32 i)
2646{
2647 return 0x0041a184 + i*16;
2648}
2649static inline u32 gr_gpccs_imemt_r(u32 i)
2650{
2651 return 0x0041a188 + i*16;
2652}
2653static inline u32 gr_gpccs_imemt__size_1_v(void)
2654{
2655 return 0x00000004;
2656}
2657static inline u32 gr_gpccs_imemt_tag_f(u32 v)
2658{
2659 return (v & 0xffff) << 0;
2660}
2661static inline u32 gr_gpccs_dmemc_r(u32 i)
2662{
2663 return 0x0041a1c0 + i*8;
2664}
2665static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
2666{
2667 return (v & 0x3f) << 2;
2668}
2669static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
2670{
2671 return (v & 0xff) << 8;
2672}
2673static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
2674{
2675 return (v & 0x1) << 24;
2676}
2677static inline u32 gr_gpccs_dmemd_r(u32 i)
2678{
2679 return 0x0041a1c4 + i*8;
2680}
2681static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
2682{
2683 return 0x0041a800 + i*4;
2684}
2685static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
2686{
2687 return (v & 0xffffffff) << 0;
2688}
2689static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
2690{
2691 return 0x00418e24;
2692}
2693static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
2694{
2695 return 32;
2696}
2697static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
2698{
2699 return (v & 0xffffffff) << 0;
2700}
2701static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
2702{
2703 return 0xffffffff << 0;
2704}
2705static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
2706{
2707 return (r >> 0) & 0xffffffff;
2708}
2709static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
2710{
2711 return 0x00000000;
2712}
2713static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
2714{
2715 return 0x0;
2716}
2717static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
2718{
2719 return 0x00418e28;
2720}
2721static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
2722{
2723 return 11;
2724}
2725static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
2726{
2727 return (v & 0x7ff) << 0;
2728}
2729static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
2730{
2731 return 0x7ff << 0;
2732}
2733static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
2734{
2735 return (r >> 0) & 0x7ff;
2736}
2737static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
2738{
2739 return 0x00000018;
2740}
2741static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
2742{
2743 return 0x18;
2744}
2745static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
2746{
2747 return 1;
2748}
2749static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
2750{
2751 return (v & 0x1) << 31;
2752}
2753static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
2754{
2755 return 0x1 << 31;
2756}
2757static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
2758{
2759 return (r >> 31) & 0x1;
2760}
2761static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
2762{
2763 return 0x00000000;
2764}
2765static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
2766{
2767 return 0x0;
2768}
2769static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
2770{
2771 return 0x00000001;
2772}
2773static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
2774{
2775 return 0x80000000;
2776}
2777static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
2778{
2779 return 0x00500ee4;
2780}
2781static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
2782{
2783 return (v & 0xffff) << 0;
2784}
2785static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
2786{
2787 return 0x00000250;
2788}
2789static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
2790{
2791 return 0x00000100;
2792}
2793static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
2794{
2795 return 0x00500ee0;
2796}
2797static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
2798{
2799 return (v & 0xffffffff) << 0;
2800}
2801static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
2802{
2803 return 0x00000008;
2804}
2805static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
2806{
2807 return 0x00418eec;
2808}
2809static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
2810{
2811 return (v & 0xfff) << 0;
2812}
2813static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
2814{
2815 return 0x00000100;
2816}
2817static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
2818{
2819 return 0x0041befc;
2820}
2821static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
2822{
2823 return (v & 0xfff) << 0;
2824}
2825static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
2826{
2827 return 0x00418ea0 + i*4;
2828}
2829static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
2830{
2831 return (v & 0x3fffff) << 0;
2832}
2833static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
2834{
2835 return 0x3fffff << 0;
2836}
2837static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
2838{
2839 return 0x00418010 + i*4;
2840}
2841static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
2842{
2843 return (v & 0xffffffff) << 0;
2844}
2845static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
2846{
2847 return 0x0041804c + i*4;
2848}
2849static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
2850{
2851 return (v & 0xffffffff) << 0;
2852}
2853static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
2854{
2855 return 0x00418088 + i*4;
2856}
2857static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
2858{
2859 return (v & 0xffffffff) << 0;
2860}
2861static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
2862{
2863 return 0x004180c4 + i*4;
2864}
2865static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
2866{
2867 return (v & 0xffffffff) << 0;
2868}
2869static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
2870{
2871 return 0x00500100;
2872}
2873static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
2874{
2875 return 0x00418110 + i*4;
2876}
2877static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
2878{
2879 return (v & 0xffffffff) << 0;
2880}
2881static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
2882{
2883 return 0x0050014c;
2884}
2885static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
2886{
2887 return 0x00418810;
2888}
2889static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
2890{
2891 return (v & 0xfffffff) << 0;
2892}
2893static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
2894{
2895 return 0x0000000c;
2896}
2897static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
2898{
2899 return 0x80000000;
2900}
2901static inline u32 gr_crstr_gpc_map0_r(void)
2902{
2903 return 0x00418b08;
2904}
2905static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
2906{
2907 return (v & 0x7) << 0;
2908}
2909static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
2910{
2911 return (v & 0x7) << 5;
2912}
2913static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
2914{
2915 return (v & 0x7) << 10;
2916}
2917static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
2918{
2919 return (v & 0x7) << 15;
2920}
2921static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
2922{
2923 return (v & 0x7) << 20;
2924}
2925static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
2926{
2927 return (v & 0x7) << 25;
2928}
2929static inline u32 gr_crstr_gpc_map1_r(void)
2930{
2931 return 0x00418b0c;
2932}
2933static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
2934{
2935 return (v & 0x7) << 0;
2936}
2937static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
2938{
2939 return (v & 0x7) << 5;
2940}
2941static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
2942{
2943 return (v & 0x7) << 10;
2944}
2945static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
2946{
2947 return (v & 0x7) << 15;
2948}
2949static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
2950{
2951 return (v & 0x7) << 20;
2952}
2953static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
2954{
2955 return (v & 0x7) << 25;
2956}
2957static inline u32 gr_crstr_gpc_map2_r(void)
2958{
2959 return 0x00418b10;
2960}
2961static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
2962{
2963 return (v & 0x7) << 0;
2964}
2965static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
2966{
2967 return (v & 0x7) << 5;
2968}
2969static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
2970{
2971 return (v & 0x7) << 10;
2972}
2973static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
2974{
2975 return (v & 0x7) << 15;
2976}
2977static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
2978{
2979 return (v & 0x7) << 20;
2980}
2981static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
2982{
2983 return (v & 0x7) << 25;
2984}
2985static inline u32 gr_crstr_gpc_map3_r(void)
2986{
2987 return 0x00418b14;
2988}
2989static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
2990{
2991 return (v & 0x7) << 0;
2992}
2993static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
2994{
2995 return (v & 0x7) << 5;
2996}
2997static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
2998{
2999 return (v & 0x7) << 10;
3000}
3001static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
3002{
3003 return (v & 0x7) << 15;
3004}
3005static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
3006{
3007 return (v & 0x7) << 20;
3008}
3009static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
3010{
3011 return (v & 0x7) << 25;
3012}
3013static inline u32 gr_crstr_gpc_map4_r(void)
3014{
3015 return 0x00418b18;
3016}
3017static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
3018{
3019 return (v & 0x7) << 0;
3020}
3021static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
3022{
3023 return (v & 0x7) << 5;
3024}
3025static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
3026{
3027 return (v & 0x7) << 10;
3028}
3029static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
3030{
3031 return (v & 0x7) << 15;
3032}
3033static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
3034{
3035 return (v & 0x7) << 20;
3036}
3037static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
3038{
3039 return (v & 0x7) << 25;
3040}
3041static inline u32 gr_crstr_gpc_map5_r(void)
3042{
3043 return 0x00418b1c;
3044}
3045static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
3046{
3047 return (v & 0x7) << 0;
3048}
3049static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
3050{
3051 return (v & 0x7) << 5;
3052}
3053static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
3054{
3055 return (v & 0x7) << 10;
3056}
3057static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
3058{
3059 return (v & 0x7) << 15;
3060}
3061static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
3062{
3063 return (v & 0x7) << 20;
3064}
3065static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
3066{
3067 return (v & 0x7) << 25;
3068}
3069static inline u32 gr_crstr_map_table_cfg_r(void)
3070{
3071 return 0x00418bb8;
3072}
3073static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
3074{
3075 return (v & 0xff) << 0;
3076}
3077static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
3078{
3079 return (v & 0xff) << 8;
3080}
3081static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
3082{
3083 return 0x00418980;
3084}
3085static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
3086{
3087 return (v & 0x7) << 0;
3088}
3089static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
3090{
3091 return (v & 0x7) << 4;
3092}
3093static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
3094{
3095 return (v & 0x7) << 8;
3096}
3097static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
3098{
3099 return (v & 0x7) << 12;
3100}
3101static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
3102{
3103 return (v & 0x7) << 16;
3104}
3105static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
3106{
3107 return (v & 0x7) << 20;
3108}
3109static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
3110{
3111 return (v & 0x7) << 24;
3112}
3113static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
3114{
3115 return (v & 0x7) << 28;
3116}
3117static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
3118{
3119 return 0x00418984;
3120}
3121static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
3122{
3123 return (v & 0x7) << 0;
3124}
3125static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
3126{
3127 return (v & 0x7) << 4;
3128}
3129static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
3130{
3131 return (v & 0x7) << 8;
3132}
3133static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
3134{
3135 return (v & 0x7) << 12;
3136}
3137static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
3138{
3139 return (v & 0x7) << 16;
3140}
3141static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
3142{
3143 return (v & 0x7) << 20;
3144}
3145static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
3146{
3147 return (v & 0x7) << 24;
3148}
3149static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
3150{
3151 return (v & 0x7) << 28;
3152}
3153static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
3154{
3155 return 0x00418988;
3156}
3157static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
3158{
3159 return (v & 0x7) << 0;
3160}
3161static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
3162{
3163 return (v & 0x7) << 4;
3164}
3165static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
3166{
3167 return (v & 0x7) << 8;
3168}
3169static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
3170{
3171 return (v & 0x7) << 12;
3172}
3173static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
3174{
3175 return (v & 0x7) << 16;
3176}
3177static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
3178{
3179 return (v & 0x7) << 20;
3180}
3181static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
3182{
3183 return (v & 0x7) << 24;
3184}
3185static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
3186{
3187 return 3;
3188}
3189static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
3190{
3191 return (v & 0x7) << 28;
3192}
3193static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
3194{
3195 return 0x7 << 28;
3196}
3197static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
3198{
3199 return (r >> 28) & 0x7;
3200}
3201static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
3202{
3203 return 0x0041898c;
3204}
3205static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
3206{
3207 return (v & 0x7) << 0;
3208}
3209static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
3210{
3211 return (v & 0x7) << 4;
3212}
3213static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
3214{
3215 return (v & 0x7) << 8;
3216}
3217static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
3218{
3219 return (v & 0x7) << 12;
3220}
3221static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
3222{
3223 return (v & 0x7) << 16;
3224}
3225static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
3226{
3227 return (v & 0x7) << 20;
3228}
3229static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
3230{
3231 return (v & 0x7) << 24;
3232}
3233static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
3234{
3235 return (v & 0x7) << 28;
3236}
3237static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
3238{
3239 return 0x00418c6c;
3240}
3241static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
3242{
3243 return 0x0;
3244}
3245static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
3246{
3247 return 0x1;
3248}
3249static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
3250{
3251 return 0x00419004;
3252}
3253static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
3254{
3255 return (v & 0xffffffff) << 0;
3256}
3257static inline u32 gr_gpcs_gcc_pagepool_r(void)
3258{
3259 return 0x00419008;
3260}
3261static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
3262{
3263 return (v & 0x3ff) << 0;
3264}
3265static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
3266{
3267 return 0x0041980c;
3268}
3269static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
3270{
3271 return 0x10;
3272}
3273static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
3274{
3275 return 0x00419848;
3276}
3277static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
3278{
3279 return (v & 0xfffffff) << 0;
3280}
3281static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
3282{
3283 return (v & 0x1) << 28;
3284}
3285static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
3286{
3287 return 0x10000000;
3288}
3289static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
3290{
3291 return 0x00419c00;
3292}
3293static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
3294{
3295 return 0x0;
3296}
3297static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
3298{
3299 return 0x8;
3300}
3301static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
3302{
3303 return 0x00419c2c;
3304}
3305static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
3306{
3307 return (v & 0xfffffff) << 0;
3308}
3309static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
3310{
3311 return (v & 0x1) << 28;
3312}
3313static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
3314{
3315 return 0x10000000;
3316}
3317static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
3318{
3319 return 0x00419e44;
3320}
3321static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
3322{
3323 return 0x2;
3324}
3325static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
3326{
3327 return 0x4;
3328}
3329static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
3330{
3331 return 0x8;
3332}
3333static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
3334{
3335 return 0x10;
3336}
3337static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
3338{
3339 return 0x20;
3340}
3341static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
3342{
3343 return 0x40;
3344}
3345static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
3346{
3347 return 0x80;
3348}
3349static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
3350{
3351 return 0x100;
3352}
3353static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
3354{
3355 return 0x200;
3356}
3357static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
3358{
3359 return 0x400;
3360}
3361static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
3362{
3363 return 0x800;
3364}
3365static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
3366{
3367 return 0x1000;
3368}
3369static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
3370{
3371 return 0x2000;
3372}
3373static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
3374{
3375 return 0x4000;
3376}
3377static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
3378{
3379 return 0x8000;
3380}
3381static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
3382{
3383 return 0x10000;
3384}
3385static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
3386{
3387 return 0x20000;
3388}
3389static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
3390{
3391 return 0x40000;
3392}
3393static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
3394{
3395 return 0x800000;
3396}
3397static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
3398{
3399 return 0x400000;
3400}
3401static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
3402{
3403 return 0x80000;
3404}
3405static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
3406{
3407 return 0x100000;
3408}
3409static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
3410{
3411 return 0x00419e4c;
3412}
3413static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
3414{
3415 return 0x1;
3416}
3417static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
3418{
3419 return 0x2;
3420}
3421static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
3422{
3423 return 0x4;
3424}
3425static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
3426{
3427 return 0x8;
3428}
3429static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
3430{
3431 return 0x10;
3432}
3433static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
3434{
3435 return 0x20000000;
3436}
3437static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
3438{
3439 return 0x40000000;
3440}
3441static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
3442{
3443 return 0x20;
3444}
3445static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
3446{
3447 return 0x40;
3448}
3449static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3450{
3451 return 0x00419d0c;
3452}
3453static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3454{
3455 return 0x2;
3456}
3457static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3458{
3459 return 0x1;
3460}
3461static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3462{
3463 return 0x0050450c;
3464}
3465static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3466{
3467 return (r >> 1) & 0x1;
3468}
3469static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3470{
3471 return 0x2;
3472}
3473static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3474{
3475 return 0x0041ac94;
3476}
3477static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3478{
3479 return (v & 0xff) << 16;
3480}
3481static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3482{
3483 return 0x00502c90;
3484}
3485static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3486{
3487 return (r >> 16) & 0xff;
3488}
3489static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3490{
3491 return 0x00000001;
3492}
3493static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3494{
3495 return 0x00504508;
3496}
3497static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3498{
3499 return (r >> 0) & 0x1;
3500}
3501static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3502{
3503 return 0x00000001;
3504}
3505static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3506{
3507 return (r >> 1) & 0x1;
3508}
3509static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3510{
3511 return 0x00000001;
3512}
3513static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
3514{
3515 return 0x00504610;
3516}
3517static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
3518{
3519 return 0x1 << 0;
3520}
3521static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
3522{
3523 return (r >> 0) & 0x1;
3524}
3525static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
3526{
3527 return 0x00000001;
3528}
3529static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
3530{
3531 return 0x00000000;
3532}
3533static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
3534{
3535 return 0x80000000;
3536}
3537static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
3538{
3539 return 0x0;
3540}
3541static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
3542{
3543 return 0x8;
3544}
3545static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
3546{
3547 return 0x0;
3548}
3549static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
3550{
3551 return 0x40000000;
3552}
3553static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
3554{
3555 return 0x1 << 1;
3556}
3557static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
3558{
3559 return (r >> 1) & 0x1;
3560}
3561static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
3562{
3563 return 0x0;
3564}
3565static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
3566{
3567 return 0x1 << 2;
3568}
3569static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
3570{
3571 return (r >> 2) & 0x1;
3572}
3573static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
3574{
3575 return 0x0;
3576}
3577static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
3578{
3579 return 0x00000000;
3580}
3581static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
3582{
3583 return 0x00000000;
3584}
3585static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3586{
3587 return 0x00504614;
3588}
3589static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3590{
3591 return 0x00504624;
3592}
3593static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3594{
3595 return 0x00504634;
3596}
3597static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3598{
3599 return 0x00419e24;
3600}
3601static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
3602{
3603 return 0x0050460c;
3604}
3605static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
3606{
3607 return (r >> 0) & 0x1;
3608}
3609static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
3610{
3611 return (r >> 4) & 0x1;
3612}
3613static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
3614{
3615 return 0x00000001;
3616}
3617static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
3618{
3619 return 0x00419e50;
3620}
3621static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
3622{
3623 return 0x10;
3624}
3625static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
3626{
3627 return 0x20;
3628}
3629static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
3630{
3631 return 0x40;
3632}
3633static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3634{
3635 return 0x1;
3636}
3637static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
3638{
3639 return 0x2;
3640}
3641static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3642{
3643 return 0x4;
3644}
3645static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3646{
3647 return 0x8;
3648}
3649static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
3650{
3651 return 0x80000000;
3652}
3653static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
3654{
3655 return 0x00504650;
3656}
3657static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
3658{
3659 return 0x10;
3660}
3661static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
3662{
3663 return 0x20000000;
3664}
3665static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
3666{
3667 return 0x40000000;
3668}
3669static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
3670{
3671 return 0x20;
3672}
3673static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
3674{
3675 return 0x40;
3676}
3677static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3678{
3679 return 0x1;
3680}
3681static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
3682{
3683 return 0x2;
3684}
3685static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3686{
3687 return 0x4;
3688}
3689static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3690{
3691 return 0x8;
3692}
3693static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
3694{
3695 return 0x80000000;
3696}
3697static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
3698{
3699 return 0x00504224;
3700}
3701static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
3702{
3703 return 0x1;
3704}
3705static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
3706{
3707 return 0x80;
3708}
3709static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
3710{
3711 return 0x100;
3712}
3713static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f(void)
3714{
3715 return 0x40000000;
3716}
3717static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
3718{
3719 return 0x00504648;
3720}
3721static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
3722{
3723 return (r >> 0) & 0xffff;
3724}
3725static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
3726{
3727 return 0x00000000;
3728}
3729static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
3730{
3731 return 0x0;
3732}
3733static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void)
3734{
3735 return 0x1 << 24;
3736}
3737static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void)
3738{
3739 return 0x7 << 25;
3740}
3741static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void)
3742{
3743 return 0x0;
3744}
3745static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
3746{
3747 return 0x00504654;
3748}
3749static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3750{
3751 return 0x00504770;
3752}
3753static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3754{
3755 return 0x00419f70;
3756}
3757static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3758{
3759 return 0x1 << 4;
3760}
3761static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3762{
3763 return (v & 0x1) << 4;
3764}
3765static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3766{
3767 return 0x0050477c;
3768}
3769static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3770{
3771 return 0x00419f7c;
3772}
3773static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3774{
3775 return 0x1 << 0;
3776}
3777static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3778{
3779 return (v & 0x1) << 0;
3780}
3781static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3782{
3783 return 0x0041be08;
3784}
3785static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3786{
3787 return 0x4;
3788}
3789static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
3790{
3791 return 0x0041bf00;
3792}
3793static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
3794{
3795 return 0x0041bf04;
3796}
3797static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
3798{
3799 return 0x0041bf08;
3800}
3801static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
3802{
3803 return 0x0041bf0c;
3804}
3805static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
3806{
3807 return 0x0041bf10;
3808}
3809static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
3810{
3811 return 0x0041bf14;
3812}
3813static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3814{
3815 return 0x0041bfd0;
3816}
3817static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3818{
3819 return (v & 0xff) << 0;
3820}
3821static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3822{
3823 return (v & 0xff) << 8;
3824}
3825static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3826{
3827 return (v & 0x1f) << 16;
3828}
3829static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3830{
3831 return (v & 0x7) << 21;
3832}
3833static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
3834{
3835 return (v & 0x1f) << 24;
3836}
3837static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3838{
3839 return 0x0041bfd4;
3840}
3841static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3842{
3843 return (v & 0xffffff) << 0;
3844}
3845static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
3846{
3847 return 0x0041bfe4;
3848}
3849static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
3850{
3851 return (v & 0x1f) << 0;
3852}
3853static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
3854{
3855 return (v & 0x1f) << 5;
3856}
3857static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
3858{
3859 return (v & 0x1f) << 10;
3860}
3861static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
3862{
3863 return (v & 0x1f) << 15;
3864}
3865static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
3866{
3867 return (v & 0x1f) << 20;
3868}
3869static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
3870{
3871 return (v & 0x1f) << 25;
3872}
3873static inline u32 gr_bes_zrop_settings_r(void)
3874{
3875 return 0x00408850;
3876}
3877static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
3878{
3879 return (v & 0xf) << 0;
3880}
3881static inline u32 gr_be0_crop_debug3_r(void)
3882{
3883 return 0x00410108;
3884}
3885static inline u32 gr_bes_crop_debug3_r(void)
3886{
3887 return 0x00408908;
3888}
3889static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
3890{
3891 return 0x1 << 31;
3892}
3893static inline u32 gr_bes_crop_settings_r(void)
3894{
3895 return 0x00408958;
3896}
3897static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
3898{
3899 return (v & 0xf) << 0;
3900}
3901static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3902{
3903 return 0x00000020;
3904}
3905static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3906{
3907 return 0x00000020;
3908}
3909static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3910{
3911 return 0x000000c0;
3912}
3913static inline u32 gr_zcull_subregion_qty_v(void)
3914{
3915 return 0x00000010;
3916}
3917static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
3918{
3919 return 0x00504604;
3920}
3921static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
3922{
3923 return 0x00504608;
3924}
3925static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
3926{
3927 return 0x0050465c;
3928}
3929static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
3930{
3931 return 0x00504660;
3932}
3933static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
3934{
3935 return 0x00504664;
3936}
3937static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
3938{
3939 return 0x00504668;
3940}
3941static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
3942{
3943 return 0x0050466c;
3944}
3945static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
3946{
3947 return 0x00504658;
3948}
3949static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
3950{
3951 return 0x00504730;
3952}
3953static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
3954{
3955 return 0x00504734;
3956}
3957static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
3958{
3959 return 0x00504738;
3960}
3961static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
3962{
3963 return 0x0050473c;
3964}
3965static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
3966{
3967 return 0x00504740;
3968}
3969static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
3970{
3971 return 0x00504744;
3972}
3973static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
3974{
3975 return 0x00504748;
3976}
3977static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
3978{
3979 return 0x0050474c;
3980}
3981static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
3982{
3983 return 0x00504678;
3984}
3985static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
3986{
3987 return 0x00504694;
3988}
3989static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
3990{
3991 return 0x005046f0;
3992}
3993static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
3994{
3995 return 0x00504700;
3996}
3997static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
3998{
3999 return 0x005046f4;
4000}
4001static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
4002{
4003 return 0x00504704;
4004}
4005static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
4006{
4007 return 0x005046f8;
4008}
4009static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
4010{
4011 return 0x00504708;
4012}
4013static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
4014{
4015 return 0x005046fc;
4016}
4017static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
4018{
4019 return 0x0050470c;
4020}
4021static inline u32 gr_fe_pwr_mode_r(void)
4022{
4023 return 0x00404170;
4024}
4025static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
4026{
4027 return 0x0;
4028}
4029static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
4030{
4031 return 0x2;
4032}
4033static inline u32 gr_fe_pwr_mode_req_v(u32 r)
4034{
4035 return (r >> 4) & 0x1;
4036}
4037static inline u32 gr_fe_pwr_mode_req_send_f(void)
4038{
4039 return 0x10;
4040}
4041static inline u32 gr_fe_pwr_mode_req_done_v(void)
4042{
4043 return 0x00000000;
4044}
4045static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
4046{
4047 return 0x00418880;
4048}
4049static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
4050{
4051 return 0x1 << 0;
4052}
4053static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
4054{
4055 return 0x1 << 11;
4056}
4057static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
4058{
4059 return 0x1 << 1;
4060}
4061static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
4062{
4063 return 0x1 << 2;
4064}
4065static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
4066{
4067 return 0x3 << 3;
4068}
4069static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
4070{
4071 return 0x3 << 5;
4072}
4073static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
4074{
4075 return 0x3 << 28;
4076}
4077static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
4078{
4079 return 0x1 << 30;
4080}
4081static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
4082{
4083 return 0x1 << 31;
4084}
4085static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
4086{
4087 return 0x00418890;
4088}
4089static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
4090{
4091 return 0x00418894;
4092}
4093static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
4094{
4095 return 0x004188b0;
4096}
4097static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
4098{
4099 return (r >> 16) & 0x1;
4100}
4101static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
4102{
4103 return 0x00000001;
4104}
4105static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
4106{
4107 return 0x004188b4;
4108}
4109static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
4110{
4111 return 0x004188b8;
4112}
4113static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
4114{
4115 return 0x004188ac;
4116}
4117static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
4118{
4119 return 0x00419e10;
4120}
4121static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
4122{
4123 return (v & 0x1) << 0;
4124}
4125static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
4126{
4127 return 0x00000001;
4128}
4129static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
4130{
4131 return 0x1 << 31;
4132}
4133static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
4134{
4135 return (r >> 31) & 0x1;
4136}
4137static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
4138{
4139 return 0x80000000;
4140}
4141static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
4142{
4143 return 0x0;
4144}
4145static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
4146{
4147 return 0x1 << 3;
4148}
4149static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
4150{
4151 return 0x8;
4152}
4153static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
4154{
4155 return 0x0;
4156}
4157static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
4158{
4159 return 0x1 << 30;
4160}
4161static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
4162{
4163 return (r >> 30) & 0x1;
4164}
4165static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
4166{
4167 return 0x40000000;
4168}
4169static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
4170{
4171 return 0x004041c0;
4172}
4173static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
4174{
4175 return (v & 0xffffffff) << 0;
4176}
4177static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
4178{
4179 return 0x0;
4180}
4181static inline u32 gr_debug_2_r(void)
4182{
4183 return 0x00400088;
4184}
4185static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_m(void)
4186{
4187 return 0x1 << 23;
4188}
4189static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_v(u32 r)
4190{
4191 return (r >> 23) & 0x1;
4192}
4193static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f(void)
4194{
4195 return 0x800000;
4196}
4197static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f(void)
4198{
4199 return 0x0;
4200}
4201static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
4202{
4203 return 0x00419c84;
4204}
4205static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
4206{
4207 return (v & 0x7) << 8;
4208}
4209static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
4210{
4211 return 0x7 << 8;
4212}
4213static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
4214{
4215 return 0x100;
4216}
4217static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
4218{
4219 return 0x00419f78;
4220}
4221static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
4222{
4223 return 0x3 << 11;
4224}
4225static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
4226{
4227 return 0x1000;
4228}
4229static inline u32 gr_gpcs_tc_debug0_r(void)
4230{
4231 return 0x00418708;
4232}
4233static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
4234{
4235 return (v & 0xff) << 0;
4236}
4237static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
4238{
4239 return 0xff << 0;
4240}
4241#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h
new file mode 100644
index 00000000..4a3f634e
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h
@@ -0,0 +1,581 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ltc_gp10b_h_
51#define _hw_ltc_gp10b_h_
52
53static inline u32 ltc_pltcg_base_v(void)
54{
55 return 0x00140000;
56}
57static inline u32 ltc_pltcg_extent_v(void)
58{
59 return 0x0017ffff;
60}
61static inline u32 ltc_ltc0_ltss_v(void)
62{
63 return 0x00140200;
64}
65static inline u32 ltc_ltc0_lts0_v(void)
66{
67 return 0x00140400;
68}
69static inline u32 ltc_ltcs_ltss_v(void)
70{
71 return 0x0017e200;
72}
73static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
74{
75 return 0x0014046c;
76}
77static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
78{
79 return 0x00140518;
80}
81static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
82{
83 return 0x0017e318;
84}
85static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
86{
87 return 0x1 << 15;
88}
89static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
90{
91 return 0x00140494;
92}
93static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
94{
95 return (r >> 0) & 0xffff;
96}
97static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
98{
99 return (r >> 16) & 0x3;
100}
101static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
102{
103 return 0x00000000;
104}
105static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
106{
107 return 0x00000001;
108}
109static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
114{
115 return 0x0017e26c;
116}
117static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
118{
119 return 0x1;
120}
121static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
122{
123 return 0x2;
124}
125static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
126{
127 return (r >> 2) & 0x1;
128}
129static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
130{
131 return 0x00000001;
132}
133static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
134{
135 return 0x4;
136}
137static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
138{
139 return 0x0014046c;
140}
141static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
142{
143 return 0x0017e270;
144}
145static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
146{
147 return (v & 0x3ffff) << 0;
148}
149static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
150{
151 return 0x0017e274;
152}
153static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
154{
155 return (v & 0x3ffff) << 0;
156}
157static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
158{
159 return 0x0003ffff;
160}
161static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
162{
163 return 0x0017e278;
164}
165static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
166{
167 return 0x0000000b;
168}
169static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
170{
171 return (r >> 0) & 0x3ffffff;
172}
173static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
174{
175 return 0x0017e27c;
176}
177static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
178{
179 return 0x0017e000;
180}
181static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
182{
183 return 0x0017e280;
184}
185static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
186{
187 return (r >> 0) & 0xffff;
188}
189static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
190{
191 return (r >> 24) & 0xf;
192}
193static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
194{
195 return (r >> 28) & 0xf;
196}
197static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
198{
199 return 0x0017e3f4;
200}
201static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
202{
203 return (r >> 0) & 0xffff;
204}
205static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
206{
207 return 0x0017e2ac;
208}
209static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
210{
211 return (v & 0x1f) << 16;
212}
213static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
214{
215 return 0x0017e338;
216}
217static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
218{
219 return (v & 0xf) << 0;
220}
221static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
222{
223 return 0x0017e33c + i*4;
224}
225static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
226{
227 return 0x00000004;
228}
229static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
230{
231 return 0x0017e34c;
232}
233static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
234{
235 return 32;
236}
237static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
238{
239 return (v & 0xffffffff) << 0;
240}
241static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
242{
243 return 0xffffffff << 0;
244}
245static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
246{
247 return (r >> 0) & 0xffffffff;
248}
249static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
250{
251 return 0x0017e2b0;
252}
253static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
254{
255 return 0x10000000;
256}
257static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
258{
259 return 0x0017e214;
260}
261static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
262{
263 return (r >> 0) & 0x1;
264}
265static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
266{
267 return 0x00000001;
268}
269static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
270{
271 return 0x1;
272}
273static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
274{
275 return 0x00140214;
276}
277static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
278{
279 return (r >> 0) & 0x1;
280}
281static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
282{
283 return 0x00000001;
284}
285static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
286{
287 return 0x1;
288}
289static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
290{
291 return 0x00142214;
292}
293static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
294{
295 return (r >> 0) & 0x1;
296}
297static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
298{
299 return 0x00000001;
300}
301static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
302{
303 return 0x1;
304}
305static inline u32 ltc_ltcs_ltss_intr_r(void)
306{
307 return 0x0017e20c;
308}
309static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
310{
311 return 0x100;
312}
313static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
314{
315 return 0x200;
316}
317static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
318{
319 return 0x1 << 20;
320}
321static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
322{
323 return 0x1 << 30;
324}
325static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
326{
327 return 0x1000000;
328}
329static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
330{
331 return 0x2000000;
332}
333static inline u32 ltc_ltc0_lts0_intr_r(void)
334{
335 return 0x0014040c;
336}
337static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
338{
339 return 0x0014051c;
340}
341static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
342{
343 return 0xff << 0;
344}
345static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
346{
347 return (r >> 0) & 0xff;
348}
349static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
350{
351 return 0xff << 16;
352}
353static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
354{
355 return (r >> 16) & 0xff;
356}
357static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
358{
359 return 0x0017e2a0;
360}
361static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
362{
363 return (r >> 0) & 0x1;
364}
365static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
366{
367 return 0x00000001;
368}
369static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
370{
371 return 0x1;
372}
373static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
374{
375 return (r >> 8) & 0xf;
376}
377static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
378{
379 return 0x00000003;
380}
381static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
382{
383 return 0x300;
384}
385static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
386{
387 return (r >> 28) & 0x1;
388}
389static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
390{
391 return 0x00000001;
392}
393static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
394{
395 return 0x10000000;
396}
397static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
398{
399 return (r >> 29) & 0x1;
400}
401static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
402{
403 return 0x00000001;
404}
405static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
406{
407 return 0x20000000;
408}
409static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
410{
411 return (r >> 30) & 0x1;
412}
413static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
414{
415 return 0x00000001;
416}
417static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
418{
419 return 0x40000000;
420}
421static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
422{
423 return 0x0017e2a4;
424}
425static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
426{
427 return (r >> 0) & 0x1;
428}
429static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
430{
431 return 0x00000001;
432}
433static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
434{
435 return 0x1;
436}
437static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
438{
439 return (r >> 8) & 0xf;
440}
441static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
442{
443 return 0x00000003;
444}
445static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
446{
447 return 0x300;
448}
449static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
450{
451 return (r >> 16) & 0x1;
452}
453static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
454{
455 return 0x00000001;
456}
457static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
458{
459 return 0x10000;
460}
461static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
462{
463 return (r >> 28) & 0x1;
464}
465static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
466{
467 return 0x00000001;
468}
469static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
470{
471 return 0x10000000;
472}
473static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
474{
475 return (r >> 29) & 0x1;
476}
477static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
478{
479 return 0x00000001;
480}
481static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
482{
483 return 0x20000000;
484}
485static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
486{
487 return (r >> 30) & 0x1;
488}
489static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
490{
491 return 0x00000001;
492}
493static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
494{
495 return 0x40000000;
496}
497static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
498{
499 return 0x001402a0;
500}
501static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
502{
503 return (r >> 0) & 0x1;
504}
505static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
506{
507 return 0x00000001;
508}
509static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
510{
511 return 0x1;
512}
513static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
514{
515 return 0x001402a4;
516}
517static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
518{
519 return (r >> 0) & 0x1;
520}
521static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
522{
523 return 0x00000001;
524}
525static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
526{
527 return 0x1;
528}
529static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
530{
531 return 0x001422a0;
532}
533static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
534{
535 return (r >> 0) & 0x1;
536}
537static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
538{
539 return 0x00000001;
540}
541static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
542{
543 return 0x1;
544}
545static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
546{
547 return 0x001422a4;
548}
549static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
550{
551 return (r >> 0) & 0x1;
552}
553static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
554{
555 return 0x00000001;
556}
557static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
558{
559 return 0x1;
560}
561static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
562{
563 return 0x0014058c;
564}
565static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
566{
567 return (r >> 0) & 0xffff;
568}
569static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
570{
571 return (r >> 16) & 0x1f;
572}
573static inline u32 ltc_ltca_g_axi_pctrl_r(void)
574{
575 return 0x00160000;
576}
577static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
578{
579 return (v & 0xff) << 2;
580}
581#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h
new file mode 100644
index 00000000..30165e66
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h
@@ -0,0 +1,245 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_mc_gp10b_h_
51#define _hw_mc_gp10b_h_
52
53static inline u32 mc_boot_0_r(void)
54{
55 return 0x00000000;
56}
57static inline u32 mc_boot_0_architecture_v(u32 r)
58{
59 return (r >> 24) & 0x1f;
60}
61static inline u32 mc_boot_0_implementation_v(u32 r)
62{
63 return (r >> 20) & 0xf;
64}
65static inline u32 mc_boot_0_major_revision_v(u32 r)
66{
67 return (r >> 4) & 0xf;
68}
69static inline u32 mc_boot_0_minor_revision_v(u32 r)
70{
71 return (r >> 0) & 0xf;
72}
73static inline u32 mc_intr_r(u32 i)
74{
75 return 0x00000100 + i*4;
76}
77static inline u32 mc_intr_pfifo_pending_f(void)
78{
79 return 0x100;
80}
81static inline u32 mc_intr_replayable_fault_pending_f(void)
82{
83 return 0x200;
84}
85static inline u32 mc_intr_pgraph_pending_f(void)
86{
87 return 0x1000;
88}
89static inline u32 mc_intr_pmu_pending_f(void)
90{
91 return 0x1000000;
92}
93static inline u32 mc_intr_ltc_pending_f(void)
94{
95 return 0x2000000;
96}
97static inline u32 mc_intr_priv_ring_pending_f(void)
98{
99 return 0x40000000;
100}
101static inline u32 mc_intr_pbus_pending_f(void)
102{
103 return 0x10000000;
104}
105static inline u32 mc_intr_en_r(u32 i)
106{
107 return 0x00000140 + i*4;
108}
109static inline u32 mc_intr_en_set_r(u32 i)
110{
111 return 0x00000160 + i*4;
112}
113static inline u32 mc_intr_en_clear_r(u32 i)
114{
115 return 0x00000180 + i*4;
116}
117static inline u32 mc_enable_r(void)
118{
119 return 0x00000200;
120}
121static inline u32 mc_enable_xbar_enabled_f(void)
122{
123 return 0x4;
124}
125static inline u32 mc_enable_l2_enabled_f(void)
126{
127 return 0x8;
128}
129static inline u32 mc_enable_pmedia_s(void)
130{
131 return 1;
132}
133static inline u32 mc_enable_pmedia_f(u32 v)
134{
135 return (v & 0x1) << 4;
136}
137static inline u32 mc_enable_pmedia_m(void)
138{
139 return 0x1 << 4;
140}
141static inline u32 mc_enable_pmedia_v(u32 r)
142{
143 return (r >> 4) & 0x1;
144}
145static inline u32 mc_enable_priv_ring_enabled_f(void)
146{
147 return 0x20;
148}
149static inline u32 mc_enable_ce0_m(void)
150{
151 return 0x1 << 6;
152}
153static inline u32 mc_enable_pfifo_enabled_f(void)
154{
155 return 0x100;
156}
157static inline u32 mc_enable_pgraph_enabled_f(void)
158{
159 return 0x1000;
160}
161static inline u32 mc_enable_pwr_v(u32 r)
162{
163 return (r >> 13) & 0x1;
164}
165static inline u32 mc_enable_pwr_disabled_v(void)
166{
167 return 0x00000000;
168}
169static inline u32 mc_enable_pwr_enabled_f(void)
170{
171 return 0x2000;
172}
173static inline u32 mc_enable_pfb_enabled_f(void)
174{
175 return 0x100000;
176}
177static inline u32 mc_enable_ce2_m(void)
178{
179 return 0x1 << 21;
180}
181static inline u32 mc_enable_ce2_enabled_f(void)
182{
183 return 0x200000;
184}
185static inline u32 mc_enable_blg_enabled_f(void)
186{
187 return 0x8000000;
188}
189static inline u32 mc_enable_perfmon_enabled_f(void)
190{
191 return 0x10000000;
192}
193static inline u32 mc_enable_hub_enabled_f(void)
194{
195 return 0x20000000;
196}
197static inline u32 mc_intr_ltc_r(void)
198{
199 return 0x000001c0;
200}
201static inline u32 mc_enable_pb_r(void)
202{
203 return 0x00000204;
204}
205static inline u32 mc_enable_pb_0_s(void)
206{
207 return 1;
208}
209static inline u32 mc_enable_pb_0_f(u32 v)
210{
211 return (v & 0x1) << 0;
212}
213static inline u32 mc_enable_pb_0_m(void)
214{
215 return 0x1 << 0;
216}
217static inline u32 mc_enable_pb_0_v(u32 r)
218{
219 return (r >> 0) & 0x1;
220}
221static inline u32 mc_enable_pb_0_enabled_v(void)
222{
223 return 0x00000001;
224}
225static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
226{
227 return (v & 0x1) << (0 + i*1);
228}
229static inline u32 mc_elpg_enable_r(void)
230{
231 return 0x0000020c;
232}
233static inline u32 mc_elpg_enable_xbar_enabled_f(void)
234{
235 return 0x4;
236}
237static inline u32 mc_elpg_enable_pfb_enabled_f(void)
238{
239 return 0x100000;
240}
241static inline u32 mc_elpg_enable_hub_enabled_f(void)
242{
243 return 0x20000000;
244}
245#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h
new file mode 100644
index 00000000..65aedccd
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h
@@ -0,0 +1,593 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pbdma_gp10b_h_
51#define _hw_pbdma_gp10b_h_
52
53static inline u32 pbdma_gp_entry1_r(void)
54{
55 return 0x10000004;
56}
57static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
58{
59 return (r >> 0) & 0xff;
60}
61static inline u32 pbdma_gp_entry1_length_f(u32 v)
62{
63 return (v & 0x1fffff) << 10;
64}
65static inline u32 pbdma_gp_entry1_length_v(u32 r)
66{
67 return (r >> 10) & 0x1fffff;
68}
69static inline u32 pbdma_gp_base_r(u32 i)
70{
71 return 0x00040048 + i*8192;
72}
73static inline u32 pbdma_gp_base__size_1_v(void)
74{
75 return 0x00000001;
76}
77static inline u32 pbdma_gp_base_offset_f(u32 v)
78{
79 return (v & 0x1fffffff) << 3;
80}
81static inline u32 pbdma_gp_base_rsvd_s(void)
82{
83 return 3;
84}
85static inline u32 pbdma_gp_base_hi_r(u32 i)
86{
87 return 0x0004004c + i*8192;
88}
89static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
90{
91 return (v & 0xff) << 0;
92}
93static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
94{
95 return (v & 0x1f) << 16;
96}
97static inline u32 pbdma_gp_fetch_r(u32 i)
98{
99 return 0x00040050 + i*8192;
100}
101static inline u32 pbdma_gp_get_r(u32 i)
102{
103 return 0x00040014 + i*8192;
104}
105static inline u32 pbdma_gp_put_r(u32 i)
106{
107 return 0x00040000 + i*8192;
108}
109static inline u32 pbdma_pb_fetch_r(u32 i)
110{
111 return 0x00040054 + i*8192;
112}
113static inline u32 pbdma_pb_fetch_hi_r(u32 i)
114{
115 return 0x00040058 + i*8192;
116}
117static inline u32 pbdma_get_r(u32 i)
118{
119 return 0x00040018 + i*8192;
120}
121static inline u32 pbdma_get_hi_r(u32 i)
122{
123 return 0x0004001c + i*8192;
124}
125static inline u32 pbdma_put_r(u32 i)
126{
127 return 0x0004005c + i*8192;
128}
129static inline u32 pbdma_put_hi_r(u32 i)
130{
131 return 0x00040060 + i*8192;
132}
133static inline u32 pbdma_formats_r(u32 i)
134{
135 return 0x0004009c + i*8192;
136}
137static inline u32 pbdma_formats_gp_fermi0_f(void)
138{
139 return 0x0;
140}
141static inline u32 pbdma_formats_pb_fermi1_f(void)
142{
143 return 0x100;
144}
145static inline u32 pbdma_formats_mp_fermi0_f(void)
146{
147 return 0x0;
148}
149static inline u32 pbdma_pb_header_r(u32 i)
150{
151 return 0x00040084 + i*8192;
152}
153static inline u32 pbdma_pb_header_priv_user_f(void)
154{
155 return 0x0;
156}
157static inline u32 pbdma_pb_header_method_zero_f(void)
158{
159 return 0x0;
160}
161static inline u32 pbdma_pb_header_subchannel_zero_f(void)
162{
163 return 0x0;
164}
165static inline u32 pbdma_pb_header_level_main_f(void)
166{
167 return 0x0;
168}
169static inline u32 pbdma_pb_header_first_true_f(void)
170{
171 return 0x400000;
172}
173static inline u32 pbdma_pb_header_type_inc_f(void)
174{
175 return 0x20000000;
176}
177static inline u32 pbdma_pb_header_type_non_inc_f(void)
178{
179 return 0x60000000;
180}
181static inline u32 pbdma_hdr_shadow_r(u32 i)
182{
183 return 0x00040118 + i*8192;
184}
185static inline u32 pbdma_subdevice_r(u32 i)
186{
187 return 0x00040094 + i*8192;
188}
189static inline u32 pbdma_subdevice_id_f(u32 v)
190{
191 return (v & 0xfff) << 0;
192}
193static inline u32 pbdma_subdevice_status_active_f(void)
194{
195 return 0x10000000;
196}
197static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
198{
199 return 0x20000000;
200}
201static inline u32 pbdma_method0_r(u32 i)
202{
203 return 0x000400c0 + i*8192;
204}
205static inline u32 pbdma_method0_fifo_size_v(void)
206{
207 return 0x00000004;
208}
209static inline u32 pbdma_method0_addr_f(u32 v)
210{
211 return (v & 0xfff) << 2;
212}
213static inline u32 pbdma_method0_addr_v(u32 r)
214{
215 return (r >> 2) & 0xfff;
216}
217static inline u32 pbdma_method0_subch_v(u32 r)
218{
219 return (r >> 16) & 0x7;
220}
221static inline u32 pbdma_method0_first_true_f(void)
222{
223 return 0x400000;
224}
225static inline u32 pbdma_method0_valid_true_f(void)
226{
227 return 0x80000000;
228}
229static inline u32 pbdma_method1_r(u32 i)
230{
231 return 0x000400c8 + i*8192;
232}
233static inline u32 pbdma_method2_r(u32 i)
234{
235 return 0x000400d0 + i*8192;
236}
237static inline u32 pbdma_method3_r(u32 i)
238{
239 return 0x000400d8 + i*8192;
240}
241static inline u32 pbdma_data0_r(u32 i)
242{
243 return 0x000400c4 + i*8192;
244}
245static inline u32 pbdma_target_r(u32 i)
246{
247 return 0x000400ac + i*8192;
248}
249static inline u32 pbdma_target_engine_sw_f(void)
250{
251 return 0x1f;
252}
253static inline u32 pbdma_acquire_r(u32 i)
254{
255 return 0x00040030 + i*8192;
256}
257static inline u32 pbdma_acquire_retry_man_2_f(void)
258{
259 return 0x2;
260}
261static inline u32 pbdma_acquire_retry_exp_2_f(void)
262{
263 return 0x100;
264}
265static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
266{
267 return (v & 0xf) << 11;
268}
269static inline u32 pbdma_acquire_timeout_exp_max_v(void)
270{
271 return 0x0000000f;
272}
273static inline u32 pbdma_acquire_timeout_exp_max_f(void)
274{
275 return 0x7800;
276}
277static inline u32 pbdma_acquire_timeout_man_f(u32 v)
278{
279 return (v & 0xffff) << 15;
280}
281static inline u32 pbdma_acquire_timeout_man_max_v(void)
282{
283 return 0x0000ffff;
284}
285static inline u32 pbdma_acquire_timeout_man_max_f(void)
286{
287 return 0x7fff8000;
288}
289static inline u32 pbdma_acquire_timeout_en_enable_f(void)
290{
291 return 0x80000000;
292}
293static inline u32 pbdma_acquire_timeout_en_disable_f(void)
294{
295 return 0x0;
296}
297static inline u32 pbdma_status_r(u32 i)
298{
299 return 0x00040100 + i*8192;
300}
301static inline u32 pbdma_channel_r(u32 i)
302{
303 return 0x00040120 + i*8192;
304}
305static inline u32 pbdma_signature_r(u32 i)
306{
307 return 0x00040010 + i*8192;
308}
309static inline u32 pbdma_signature_hw_valid_f(void)
310{
311 return 0xface;
312}
313static inline u32 pbdma_signature_sw_zero_f(void)
314{
315 return 0x0;
316}
317static inline u32 pbdma_userd_r(u32 i)
318{
319 return 0x00040008 + i*8192;
320}
321static inline u32 pbdma_userd_target_vid_mem_f(void)
322{
323 return 0x0;
324}
325static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
326{
327 return 0x2;
328}
329static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
330{
331 return 0x3;
332}
333static inline u32 pbdma_userd_addr_f(u32 v)
334{
335 return (v & 0x7fffff) << 9;
336}
337static inline u32 pbdma_userd_hi_r(u32 i)
338{
339 return 0x0004000c + i*8192;
340}
341static inline u32 pbdma_userd_hi_addr_f(u32 v)
342{
343 return (v & 0xff) << 0;
344}
345static inline u32 pbdma_config_r(u32 i)
346{
347 return 0x000400f4 + i*8192;
348}
349static inline u32 pbdma_config_auth_level_privileged_f(void)
350{
351 return 0x100;
352}
353static inline u32 pbdma_hce_ctrl_r(u32 i)
354{
355 return 0x000400e4 + i*8192;
356}
357static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
358{
359 return 0x20;
360}
361static inline u32 pbdma_intr_0_r(u32 i)
362{
363 return 0x00040108 + i*8192;
364}
365static inline u32 pbdma_intr_0_memreq_v(u32 r)
366{
367 return (r >> 0) & 0x1;
368}
369static inline u32 pbdma_intr_0_memreq_pending_f(void)
370{
371 return 0x1;
372}
373static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
374{
375 return 0x2;
376}
377static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
378{
379 return 0x4;
380}
381static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
382{
383 return 0x8;
384}
385static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
386{
387 return 0x10;
388}
389static inline u32 pbdma_intr_0_memflush_pending_f(void)
390{
391 return 0x20;
392}
393static inline u32 pbdma_intr_0_memop_pending_f(void)
394{
395 return 0x40;
396}
397static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
398{
399 return 0x80;
400}
401static inline u32 pbdma_intr_0_lbreq_pending_f(void)
402{
403 return 0x100;
404}
405static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
406{
407 return 0x200;
408}
409static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
410{
411 return 0x400;
412}
413static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
414{
415 return 0x800;
416}
417static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
418{
419 return 0x1000;
420}
421static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
422{
423 return 0x2000;
424}
425static inline u32 pbdma_intr_0_gpptr_pending_f(void)
426{
427 return 0x4000;
428}
429static inline u32 pbdma_intr_0_gpentry_pending_f(void)
430{
431 return 0x8000;
432}
433static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
434{
435 return 0x10000;
436}
437static inline u32 pbdma_intr_0_pbptr_pending_f(void)
438{
439 return 0x20000;
440}
441static inline u32 pbdma_intr_0_pbentry_pending_f(void)
442{
443 return 0x40000;
444}
445static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
446{
447 return 0x80000;
448}
449static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
450{
451 return 0x100000;
452}
453static inline u32 pbdma_intr_0_method_pending_f(void)
454{
455 return 0x200000;
456}
457static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
458{
459 return 0x400000;
460}
461static inline u32 pbdma_intr_0_device_pending_f(void)
462{
463 return 0x800000;
464}
465static inline u32 pbdma_intr_0_semaphore_pending_f(void)
466{
467 return 0x2000000;
468}
469static inline u32 pbdma_intr_0_acquire_pending_f(void)
470{
471 return 0x4000000;
472}
473static inline u32 pbdma_intr_0_pri_pending_f(void)
474{
475 return 0x8000000;
476}
477static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
478{
479 return 0x20000000;
480}
481static inline u32 pbdma_intr_0_pbseg_pending_f(void)
482{
483 return 0x40000000;
484}
485static inline u32 pbdma_intr_0_signature_pending_f(void)
486{
487 return 0x80000000;
488}
489static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
490{
491 return 0x10000000;
492}
493static inline u32 pbdma_intr_1_r(u32 i)
494{
495 return 0x00040148 + i*8192;
496}
497static inline u32 pbdma_intr_en_0_r(u32 i)
498{
499 return 0x0004010c + i*8192;
500}
501static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
502{
503 return 0x100;
504}
505static inline u32 pbdma_intr_en_1_r(u32 i)
506{
507 return 0x0004014c + i*8192;
508}
509static inline u32 pbdma_intr_stall_r(u32 i)
510{
511 return 0x0004013c + i*8192;
512}
513static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
514{
515 return 0x100;
516}
517static inline u32 pbdma_udma_nop_r(void)
518{
519 return 0x00000008;
520}
521static inline u32 pbdma_allowed_syncpoints_r(u32 i)
522{
523 return 0x000400e8 + i*8192;
524}
525static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v)
526{
527 return (v & 0x1) << 31;
528}
529static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v)
530{
531 return (v & 0x7fff) << 16;
532}
533static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r)
534{
535 return (r >> 16) & 0x7fff;
536}
537static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v)
538{
539 return (v & 0x1) << 15;
540}
541static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
542{
543 return (v & 0x7fff) << 0;
544}
545static inline u32 pbdma_syncpointa_r(u32 i)
546{
547 return 0x000400a4 + i*8192;
548}
549static inline u32 pbdma_syncpointa_payload_v(u32 r)
550{
551 return (r >> 0) & 0xffffffff;
552}
553static inline u32 pbdma_syncpointb_r(u32 i)
554{
555 return 0x000400a8 + i*8192;
556}
557static inline u32 pbdma_syncpointb_op_v(u32 r)
558{
559 return (r >> 0) & 0x1;
560}
561static inline u32 pbdma_syncpointb_op_wait_v(void)
562{
563 return 0x00000000;
564}
565static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
566{
567 return (r >> 4) & 0x1;
568}
569static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
570{
571 return 0x00000001;
572}
573static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
574{
575 return (r >> 8) & 0xfff;
576}
577static inline u32 pbdma_runlist_timeslice_r(u32 i)
578{
579 return 0x000400f8 + i*8192;
580}
581static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
582{
583 return 0x80;
584}
585static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
586{
587 return 0x3000;
588}
589static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
590{
591 return 0x10000000;
592}
593#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h
new file mode 100644
index 00000000..ea1a61d2
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h
@@ -0,0 +1,205 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_perf_gp10b_h_
51#define _hw_perf_gp10b_h_
52
53static inline u32 perf_pmasys_control_r(void)
54{
55 return 0x001b4000;
56}
57static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
58{
59 return (r >> 4) & 0x1;
60}
61static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
66{
67 return 0x10;
68}
69static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
70{
71 return (v & 0x1) << 5;
72}
73static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
74{
75 return (r >> 5) & 0x1;
76}
77static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
82{
83 return 0x20;
84}
85static inline u32 perf_pmasys_mem_block_r(void)
86{
87 return 0x001b4070;
88}
89static inline u32 perf_pmasys_mem_block_base_f(u32 v)
90{
91 return (v & 0xfffffff) << 0;
92}
93static inline u32 perf_pmasys_mem_block_target_f(u32 v)
94{
95 return (v & 0x3) << 28;
96}
97static inline u32 perf_pmasys_mem_block_target_v(u32 r)
98{
99 return (r >> 28) & 0x3;
100}
101static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
102{
103 return 0x00000000;
104}
105static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
106{
107 return 0x0;
108}
109static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
114{
115 return 0x20000000;
116}
117static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
118{
119 return 0x00000003;
120}
121static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
122{
123 return 0x30000000;
124}
125static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
126{
127 return (v & 0x1) << 31;
128}
129static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
130{
131 return (r >> 31) & 0x1;
132}
133static inline u32 perf_pmasys_mem_block_valid_true_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 perf_pmasys_mem_block_valid_true_f(void)
138{
139 return 0x80000000;
140}
141static inline u32 perf_pmasys_mem_block_valid_false_v(void)
142{
143 return 0x00000000;
144}
145static inline u32 perf_pmasys_mem_block_valid_false_f(void)
146{
147 return 0x0;
148}
149static inline u32 perf_pmasys_outbase_r(void)
150{
151 return 0x001b4074;
152}
153static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
154{
155 return (v & 0x7ffffff) << 5;
156}
157static inline u32 perf_pmasys_outbaseupper_r(void)
158{
159 return 0x001b4078;
160}
161static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
162{
163 return (v & 0xff) << 0;
164}
165static inline u32 perf_pmasys_outsize_r(void)
166{
167 return 0x001b407c;
168}
169static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
170{
171 return (v & 0x7ffffff) << 5;
172}
173static inline u32 perf_pmasys_mem_bytes_r(void)
174{
175 return 0x001b4084;
176}
177static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
178{
179 return (v & 0xfffffff) << 4;
180}
181static inline u32 perf_pmasys_mem_bump_r(void)
182{
183 return 0x001b4088;
184}
185static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
186{
187 return (v & 0xfffffff) << 4;
188}
189static inline u32 perf_pmasys_enginestatus_r(void)
190{
191 return 0x001b40a4;
192}
193static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
194{
195 return (v & 0x1) << 4;
196}
197static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
198{
199 return 0x00000001;
200}
201static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
202{
203 return 0x10;
204}
205#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pram_gp10b.h
new file mode 100644
index 00000000..12a83a71
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_pram_gp10b.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pram_gp10b_h_
51#define _hw_pram_gp10b_h_
52
53static inline u32 pram_data032_r(u32 i)
54{
55 return 0x00700000 + i*4;
56}
57#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h
new file mode 100644
index 00000000..7a458858
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringmaster_gp10b_h_
51#define _hw_pri_ringmaster_gp10b_h_
52
53static inline u32 pri_ringmaster_command_r(void)
54{
55 return 0x0012004c;
56}
57static inline u32 pri_ringmaster_command_cmd_m(void)
58{
59 return 0x3f << 0;
60}
61static inline u32 pri_ringmaster_command_cmd_v(u32 r)
62{
63 return (r >> 0) & 0x3f;
64}
65static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
66{
67 return 0x00000000;
68}
69static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
70{
71 return 0x1;
72}
73static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
74{
75 return 0x2;
76}
77static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
78{
79 return 0x3;
80}
81static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
82{
83 return 0x0;
84}
85static inline u32 pri_ringmaster_command_data_r(void)
86{
87 return 0x00120048;
88}
89static inline u32 pri_ringmaster_start_results_r(void)
90{
91 return 0x00120050;
92}
93static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
98{
99 return 0x00000001;
100}
101static inline u32 pri_ringmaster_intr_status0_r(void)
102{
103 return 0x00120058;
104}
105static inline u32 pri_ringmaster_intr_status1_r(void)
106{
107 return 0x0012005c;
108}
109static inline u32 pri_ringmaster_global_ctl_r(void)
110{
111 return 0x00120060;
112}
113static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
114{
115 return 0x1;
116}
117static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
118{
119 return 0x0;
120}
121static inline u32 pri_ringmaster_enum_fbp_r(void)
122{
123 return 0x00120074;
124}
125static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
126{
127 return (r >> 0) & 0x1f;
128}
129static inline u32 pri_ringmaster_enum_gpc_r(void)
130{
131 return 0x00120078;
132}
133static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
134{
135 return (r >> 0) & 0x1f;
136}
137static inline u32 pri_ringmaster_enum_ltc_r(void)
138{
139 return 0x0012006c;
140}
141static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
142{
143 return (r >> 0) & 0x1f;
144}
145#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h
new file mode 100644
index 00000000..eb711452
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_sys_gp10b_h_
51#define _hw_pri_ringstation_sys_gp10b_h_
52
53static inline u32 pri_ringstation_sys_master_config_r(u32 i)
54{
55 return 0x00122300 + i*4;
56}
57static inline u32 pri_ringstation_sys_decode_config_r(void)
58{
59 return 0x00122204;
60}
61static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
62{
63 return 0x7 << 0;
64}
65static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
66{
67 return 0x1;
68}
69#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h
new file mode 100644
index 00000000..3392242c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h
@@ -0,0 +1,165 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_proj_gp10b_h_
51#define _hw_proj_gp10b_h_
52
53static inline u32 proj_gpc_base_v(void)
54{
55 return 0x00500000;
56}
57static inline u32 proj_gpc_shared_base_v(void)
58{
59 return 0x00418000;
60}
61static inline u32 proj_gpc_stride_v(void)
62{
63 return 0x00008000;
64}
65static inline u32 proj_ltc_stride_v(void)
66{
67 return 0x00002000;
68}
69static inline u32 proj_lts_stride_v(void)
70{
71 return 0x00000200;
72}
73static inline u32 proj_fbpa_base_v(void)
74{
75 return 0x00900000;
76}
77static inline u32 proj_fbpa_shared_base_v(void)
78{
79 return 0x009a0000;
80}
81static inline u32 proj_fbpa_stride_v(void)
82{
83 return 0x00004000;
84}
85static inline u32 proj_ppc_in_gpc_base_v(void)
86{
87 return 0x00003000;
88}
89static inline u32 proj_ppc_in_gpc_shared_base_v(void)
90{
91 return 0x00003e00;
92}
93static inline u32 proj_ppc_in_gpc_stride_v(void)
94{
95 return 0x00000200;
96}
97static inline u32 proj_rop_base_v(void)
98{
99 return 0x00410000;
100}
101static inline u32 proj_rop_shared_base_v(void)
102{
103 return 0x00408800;
104}
105static inline u32 proj_rop_stride_v(void)
106{
107 return 0x00000400;
108}
109static inline u32 proj_tpc_in_gpc_base_v(void)
110{
111 return 0x00004000;
112}
113static inline u32 proj_tpc_in_gpc_stride_v(void)
114{
115 return 0x00000800;
116}
117static inline u32 proj_tpc_in_gpc_shared_base_v(void)
118{
119 return 0x00001800;
120}
121static inline u32 proj_host_num_engines_v(void)
122{
123 return 0x00000002;
124}
125static inline u32 proj_host_num_pbdma_v(void)
126{
127 return 0x00000001;
128}
129static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
130{
131 return 0x00000002;
132}
133static inline u32 proj_scal_litter_num_fbps_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 proj_scal_litter_num_fbpas_v(void)
138{
139 return 0x00000001;
140}
141static inline u32 proj_scal_litter_num_gpcs_v(void)
142{
143 return 0x00000001;
144}
145static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
146{
147 return 0x00000001;
148}
149static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
150{
151 return 0x00000002;
152}
153static inline u32 proj_scal_litter_num_zcull_banks_v(void)
154{
155 return 0x00000004;
156}
157static inline u32 proj_scal_max_gpcs_v(void)
158{
159 return 0x00000020;
160}
161static inline u32 proj_scal_max_tpc_per_gpc_v(void)
162{
163 return 0x00000008;
164}
165#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h
new file mode 100644
index 00000000..9a3591c7
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h
@@ -0,0 +1,825 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pwr_gp10b_h_
51#define _hw_pwr_gp10b_h_
52
53static inline u32 pwr_falcon_irqsset_r(void)
54{
55 return 0x0010a000;
56}
57static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
58{
59 return 0x40;
60}
61static inline u32 pwr_falcon_irqsclr_r(void)
62{
63 return 0x0010a004;
64}
65static inline u32 pwr_falcon_irqstat_r(void)
66{
67 return 0x0010a008;
68}
69static inline u32 pwr_falcon_irqstat_halt_true_f(void)
70{
71 return 0x10;
72}
73static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
74{
75 return 0x20;
76}
77static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
78{
79 return 0x40;
80}
81static inline u32 pwr_falcon_irqmode_r(void)
82{
83 return 0x0010a00c;
84}
85static inline u32 pwr_falcon_irqmset_r(void)
86{
87 return 0x0010a010;
88}
89static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
90{
91 return (v & 0x1) << 0;
92}
93static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
94{
95 return (v & 0x1) << 1;
96}
97static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
98{
99 return (v & 0x1) << 2;
100}
101static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
102{
103 return (v & 0x1) << 3;
104}
105static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
106{
107 return (v & 0x1) << 4;
108}
109static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
110{
111 return (v & 0x1) << 5;
112}
113static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
114{
115 return (v & 0x1) << 6;
116}
117static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
118{
119 return (v & 0x1) << 7;
120}
121static inline u32 pwr_falcon_irqmclr_r(void)
122{
123 return 0x0010a014;
124}
125static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
126{
127 return (v & 0x1) << 0;
128}
129static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
130{
131 return (v & 0x1) << 1;
132}
133static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
134{
135 return (v & 0x1) << 2;
136}
137static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
138{
139 return (v & 0x1) << 3;
140}
141static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
142{
143 return (v & 0x1) << 4;
144}
145static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
146{
147 return (v & 0x1) << 5;
148}
149static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
150{
151 return (v & 0x1) << 6;
152}
153static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
154{
155 return (v & 0x1) << 7;
156}
157static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
158{
159 return (v & 0xff) << 8;
160}
161static inline u32 pwr_falcon_irqmask_r(void)
162{
163 return 0x0010a018;
164}
165static inline u32 pwr_falcon_irqdest_r(void)
166{
167 return 0x0010a01c;
168}
169static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
170{
171 return (v & 0x1) << 0;
172}
173static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
174{
175 return (v & 0x1) << 1;
176}
177static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
178{
179 return (v & 0x1) << 2;
180}
181static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
182{
183 return (v & 0x1) << 3;
184}
185static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
186{
187 return (v & 0x1) << 4;
188}
189static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
190{
191 return (v & 0x1) << 5;
192}
193static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
194{
195 return (v & 0x1) << 6;
196}
197static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
198{
199 return (v & 0x1) << 7;
200}
201static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
202{
203 return (v & 0xff) << 8;
204}
205static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
206{
207 return (v & 0x1) << 16;
208}
209static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
210{
211 return (v & 0x1) << 17;
212}
213static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
214{
215 return (v & 0x1) << 18;
216}
217static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
218{
219 return (v & 0x1) << 19;
220}
221static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
222{
223 return (v & 0x1) << 20;
224}
225static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
226{
227 return (v & 0x1) << 21;
228}
229static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
230{
231 return (v & 0x1) << 22;
232}
233static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
234{
235 return (v & 0x1) << 23;
236}
237static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
238{
239 return (v & 0xff) << 24;
240}
241static inline u32 pwr_falcon_curctx_r(void)
242{
243 return 0x0010a050;
244}
245static inline u32 pwr_falcon_nxtctx_r(void)
246{
247 return 0x0010a054;
248}
249static inline u32 pwr_falcon_mailbox0_r(void)
250{
251 return 0x0010a040;
252}
253static inline u32 pwr_falcon_mailbox1_r(void)
254{
255 return 0x0010a044;
256}
257static inline u32 pwr_falcon_itfen_r(void)
258{
259 return 0x0010a048;
260}
261static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
262{
263 return 0x1;
264}
265static inline u32 pwr_falcon_idlestate_r(void)
266{
267 return 0x0010a04c;
268}
269static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
270{
271 return (r >> 0) & 0x1;
272}
273static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
274{
275 return (r >> 1) & 0x7fff;
276}
277static inline u32 pwr_falcon_os_r(void)
278{
279 return 0x0010a080;
280}
281static inline u32 pwr_falcon_engctl_r(void)
282{
283 return 0x0010a0a4;
284}
285static inline u32 pwr_falcon_cpuctl_r(void)
286{
287 return 0x0010a100;
288}
289static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
290{
291 return (v & 0x1) << 1;
292}
293static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
294{
295 return (v & 0x1) << 4;
296}
297static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
298{
299 return 0x1 << 4;
300}
301static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
302{
303 return (r >> 4) & 0x1;
304}
305static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
306{
307 return (v & 0x1) << 6;
308}
309static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
310{
311 return 0x1 << 6;
312}
313static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
314{
315 return (r >> 6) & 0x1;
316}
317static inline u32 pwr_falcon_cpuctl_alias_r(void)
318{
319 return 0x0010a130;
320}
321static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
322{
323 return (v & 0x1) << 1;
324}
325static inline u32 pwr_pmu_scpctl_stat_r(void)
326{
327 return 0x0010ac08;
328}
329static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
330{
331 return (v & 0x1) << 20;
332}
333static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
334{
335 return 0x1 << 20;
336}
337static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
338{
339 return (r >> 20) & 0x1;
340}
341static inline u32 pwr_falcon_imemc_r(u32 i)
342{
343 return 0x0010a180 + i*16;
344}
345static inline u32 pwr_falcon_imemc_offs_f(u32 v)
346{
347 return (v & 0x3f) << 2;
348}
349static inline u32 pwr_falcon_imemc_blk_f(u32 v)
350{
351 return (v & 0xff) << 8;
352}
353static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
354{
355 return (v & 0x1) << 24;
356}
357static inline u32 pwr_falcon_imemd_r(u32 i)
358{
359 return 0x0010a184 + i*16;
360}
361static inline u32 pwr_falcon_imemt_r(u32 i)
362{
363 return 0x0010a188 + i*16;
364}
365static inline u32 pwr_falcon_sctl_r(void)
366{
367 return 0x0010a240;
368}
369static inline u32 pwr_falcon_mmu_phys_sec_r(void)
370{
371 return 0x00100ce4;
372}
373static inline u32 pwr_falcon_bootvec_r(void)
374{
375 return 0x0010a104;
376}
377static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
378{
379 return (v & 0xffffffff) << 0;
380}
381static inline u32 pwr_falcon_dmactl_r(void)
382{
383 return 0x0010a10c;
384}
385static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
386{
387 return 0x1 << 1;
388}
389static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
390{
391 return 0x1 << 2;
392}
393static inline u32 pwr_falcon_hwcfg_r(void)
394{
395 return 0x0010a108;
396}
397static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
398{
399 return (r >> 0) & 0x1ff;
400}
401static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
402{
403 return (r >> 9) & 0x1ff;
404}
405static inline u32 pwr_falcon_dmatrfbase_r(void)
406{
407 return 0x0010a110;
408}
409static inline u32 pwr_falcon_dmatrfbase1_r(void)
410{
411 return 0x0010a128;
412}
413static inline u32 pwr_falcon_dmatrfmoffs_r(void)
414{
415 return 0x0010a114;
416}
417static inline u32 pwr_falcon_dmatrfcmd_r(void)
418{
419 return 0x0010a118;
420}
421static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
422{
423 return (v & 0x1) << 4;
424}
425static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
426{
427 return (v & 0x1) << 5;
428}
429static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
430{
431 return (v & 0x7) << 8;
432}
433static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
434{
435 return (v & 0x7) << 12;
436}
437static inline u32 pwr_falcon_dmatrffboffs_r(void)
438{
439 return 0x0010a11c;
440}
441static inline u32 pwr_falcon_exterraddr_r(void)
442{
443 return 0x0010a168;
444}
445static inline u32 pwr_falcon_exterrstat_r(void)
446{
447 return 0x0010a16c;
448}
449static inline u32 pwr_falcon_exterrstat_valid_m(void)
450{
451 return 0x1 << 31;
452}
453static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
454{
455 return (r >> 31) & 0x1;
456}
457static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
458{
459 return 0x00000001;
460}
461static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
462{
463 return 0x0010a200;
464}
465static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
466{
467 return 4;
468}
469static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
470{
471 return (v & 0xf) << 0;
472}
473static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
474{
475 return 0xf << 0;
476}
477static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
478{
479 return (r >> 0) & 0xf;
480}
481static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
482{
483 return 0x8;
484}
485static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
486{
487 return 0xe;
488}
489static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
490{
491 return (v & 0x1f) << 8;
492}
493static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
494{
495 return 0x0010a20c;
496}
497static inline u32 pwr_falcon_dmemc_r(u32 i)
498{
499 return 0x0010a1c0 + i*8;
500}
501static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
502{
503 return (v & 0x3f) << 2;
504}
505static inline u32 pwr_falcon_dmemc_offs_m(void)
506{
507 return 0x3f << 2;
508}
509static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
510{
511 return (v & 0xff) << 8;
512}
513static inline u32 pwr_falcon_dmemc_blk_m(void)
514{
515 return 0xff << 8;
516}
517static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
518{
519 return (v & 0x1) << 24;
520}
521static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
522{
523 return (v & 0x1) << 25;
524}
525static inline u32 pwr_falcon_dmemd_r(u32 i)
526{
527 return 0x0010a1c4 + i*8;
528}
529static inline u32 pwr_pmu_new_instblk_r(void)
530{
531 return 0x0010a480;
532}
533static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
534{
535 return (v & 0xfffffff) << 0;
536}
537static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
538{
539 return 0x0;
540}
541static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
542{
543 return 0x20000000;
544}
545static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
546{
547 return 0x30000000;
548}
549static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
550{
551 return (v & 0x1) << 30;
552}
553static inline u32 pwr_pmu_mutex_id_r(void)
554{
555 return 0x0010a488;
556}
557static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
558{
559 return (r >> 0) & 0xff;
560}
561static inline u32 pwr_pmu_mutex_id_value_init_v(void)
562{
563 return 0x00000000;
564}
565static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
566{
567 return 0x000000ff;
568}
569static inline u32 pwr_pmu_mutex_id_release_r(void)
570{
571 return 0x0010a48c;
572}
573static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
574{
575 return (v & 0xff) << 0;
576}
577static inline u32 pwr_pmu_mutex_id_release_value_m(void)
578{
579 return 0xff << 0;
580}
581static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
582{
583 return 0x00000000;
584}
585static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
586{
587 return 0x0;
588}
589static inline u32 pwr_pmu_mutex_r(u32 i)
590{
591 return 0x0010a580 + i*4;
592}
593static inline u32 pwr_pmu_mutex__size_1_v(void)
594{
595 return 0x00000010;
596}
597static inline u32 pwr_pmu_mutex_value_f(u32 v)
598{
599 return (v & 0xff) << 0;
600}
601static inline u32 pwr_pmu_mutex_value_v(u32 r)
602{
603 return (r >> 0) & 0xff;
604}
605static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
606{
607 return 0x0;
608}
609static inline u32 pwr_pmu_queue_head_r(u32 i)
610{
611 return 0x0010a4a0 + i*4;
612}
613static inline u32 pwr_pmu_queue_head__size_1_v(void)
614{
615 return 0x00000004;
616}
617static inline u32 pwr_pmu_queue_head_address_f(u32 v)
618{
619 return (v & 0xffffffff) << 0;
620}
621static inline u32 pwr_pmu_queue_head_address_v(u32 r)
622{
623 return (r >> 0) & 0xffffffff;
624}
625static inline u32 pwr_pmu_queue_tail_r(u32 i)
626{
627 return 0x0010a4b0 + i*4;
628}
629static inline u32 pwr_pmu_queue_tail__size_1_v(void)
630{
631 return 0x00000004;
632}
633static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
634{
635 return (v & 0xffffffff) << 0;
636}
637static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
638{
639 return (r >> 0) & 0xffffffff;
640}
641static inline u32 pwr_pmu_msgq_head_r(void)
642{
643 return 0x0010a4c8;
644}
645static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
646{
647 return (v & 0xffffffff) << 0;
648}
649static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
650{
651 return (r >> 0) & 0xffffffff;
652}
653static inline u32 pwr_pmu_msgq_tail_r(void)
654{
655 return 0x0010a4cc;
656}
657static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
658{
659 return (v & 0xffffffff) << 0;
660}
661static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
662{
663 return (r >> 0) & 0xffffffff;
664}
665static inline u32 pwr_pmu_idle_mask_r(u32 i)
666{
667 return 0x0010a504 + i*16;
668}
669static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
670{
671 return 0x1;
672}
673static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
674{
675 return 0x200000;
676}
677static inline u32 pwr_pmu_idle_count_r(u32 i)
678{
679 return 0x0010a508 + i*16;
680}
681static inline u32 pwr_pmu_idle_count_value_f(u32 v)
682{
683 return (v & 0x7fffffff) << 0;
684}
685static inline u32 pwr_pmu_idle_count_value_v(u32 r)
686{
687 return (r >> 0) & 0x7fffffff;
688}
689static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
690{
691 return (v & 0x1) << 31;
692}
693static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
694{
695 return 0x0010a50c + i*16;
696}
697static inline u32 pwr_pmu_idle_ctrl_value_m(void)
698{
699 return 0x3 << 0;
700}
701static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
702{
703 return 0x2;
704}
705static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
706{
707 return 0x3;
708}
709static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
710{
711 return 0x1 << 2;
712}
713static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
714{
715 return 0x0;
716}
717static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
718{
719 return 0x0010a9f0 + i*8;
720}
721static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
722{
723 return 0x0010a9f4 + i*8;
724}
725static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
726{
727 return 0x0010aa30 + i*8;
728}
729static inline u32 pwr_pmu_debug_r(u32 i)
730{
731 return 0x0010a5c0 + i*4;
732}
733static inline u32 pwr_pmu_debug__size_1_v(void)
734{
735 return 0x00000004;
736}
737static inline u32 pwr_pmu_mailbox_r(u32 i)
738{
739 return 0x0010a450 + i*4;
740}
741static inline u32 pwr_pmu_mailbox__size_1_v(void)
742{
743 return 0x0000000c;
744}
745static inline u32 pwr_pmu_bar0_addr_r(void)
746{
747 return 0x0010a7a0;
748}
749static inline u32 pwr_pmu_bar0_data_r(void)
750{
751 return 0x0010a7a4;
752}
753static inline u32 pwr_pmu_bar0_ctl_r(void)
754{
755 return 0x0010a7ac;
756}
757static inline u32 pwr_pmu_bar0_timeout_r(void)
758{
759 return 0x0010a7a8;
760}
761static inline u32 pwr_pmu_bar0_fecs_error_r(void)
762{
763 return 0x0010a988;
764}
765static inline u32 pwr_pmu_bar0_error_status_r(void)
766{
767 return 0x0010a7b0;
768}
769static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
770{
771 return 0x0010a6c0 + i*4;
772}
773static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
774{
775 return 0x0010a6e8 + i*4;
776}
777static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
778{
779 return 0x0010a710 + i*4;
780}
781static inline u32 pwr_pmu_pg_intren_r(u32 i)
782{
783 return 0x0010a760 + i*4;
784}
785static inline u32 pwr_fbif_transcfg_r(u32 i)
786{
787 return 0x0010ae00 + i*4;
788}
789static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
790{
791 return 0x0;
792}
793static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
794{
795 return 0x1;
796}
797static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
798{
799 return 0x2;
800}
801static inline u32 pwr_fbif_transcfg_mem_type_s(void)
802{
803 return 1;
804}
805static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
806{
807 return (v & 0x1) << 2;
808}
809static inline u32 pwr_fbif_transcfg_mem_type_m(void)
810{
811 return 0x1 << 2;
812}
813static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
814{
815 return (r >> 2) & 0x1;
816}
817static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
818{
819 return 0x0;
820}
821static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
822{
823 return 0x4;
824}
825#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h
new file mode 100644
index 00000000..89dfbc21
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h
@@ -0,0 +1,493 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ram_gp10b_h_
51#define _hw_ram_gp10b_h_
52
53static inline u32 ram_in_ramfc_s(void)
54{
55 return 4096;
56}
57static inline u32 ram_in_ramfc_w(void)
58{
59 return 0;
60}
61static inline u32 ram_in_page_dir_base_target_f(u32 v)
62{
63 return (v & 0x3) << 0;
64}
65static inline u32 ram_in_page_dir_base_target_w(void)
66{
67 return 128;
68}
69static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
70{
71 return 0x0;
72}
73static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
74{
75 return 0x2;
76}
77static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
78{
79 return 0x3;
80}
81static inline u32 ram_in_page_dir_base_vol_w(void)
82{
83 return 128;
84}
85static inline u32 ram_in_page_dir_base_vol_true_f(void)
86{
87 return 0x4;
88}
89static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
90{
91 return (v & 0x1) << 4;
92}
93static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
94{
95 return 0x1 << 4;
96}
97static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
98{
99 return 128;
100}
101static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
102{
103 return 0x10;
104}
105static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
106{
107 return (v & 0x1) << 5;
108}
109static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
110{
111 return 0x1 << 5;
112}
113static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
114{
115 return 128;
116}
117static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
118{
119 return 0x20;
120}
121static inline u32 ram_in_big_page_size_f(u32 v)
122{
123 return (v & 0x1) << 11;
124}
125static inline u32 ram_in_big_page_size_m(void)
126{
127 return 0x1 << 11;
128}
129static inline u32 ram_in_big_page_size_w(void)
130{
131 return 128;
132}
133static inline u32 ram_in_big_page_size_128kb_f(void)
134{
135 return 0x0;
136}
137static inline u32 ram_in_big_page_size_64kb_f(void)
138{
139 return 0x800;
140}
141static inline u32 ram_in_page_dir_base_lo_f(u32 v)
142{
143 return (v & 0xfffff) << 12;
144}
145static inline u32 ram_in_page_dir_base_lo_w(void)
146{
147 return 128;
148}
149static inline u32 ram_in_page_dir_base_hi_f(u32 v)
150{
151 return (v & 0xff) << 0;
152}
153static inline u32 ram_in_page_dir_base_hi_w(void)
154{
155 return 129;
156}
157static inline u32 ram_in_adr_limit_lo_f(u32 v)
158{
159 return (v & 0xfffff) << 12;
160}
161static inline u32 ram_in_adr_limit_lo_w(void)
162{
163 return 130;
164}
165static inline u32 ram_in_adr_limit_hi_f(u32 v)
166{
167 return (v & 0xffffffff) << 0;
168}
169static inline u32 ram_in_adr_limit_hi_w(void)
170{
171 return 131;
172}
173static inline u32 ram_in_engine_cs_w(void)
174{
175 return 132;
176}
177static inline u32 ram_in_engine_cs_wfi_v(void)
178{
179 return 0x00000000;
180}
181static inline u32 ram_in_engine_cs_wfi_f(void)
182{
183 return 0x0;
184}
185static inline u32 ram_in_engine_cs_fg_v(void)
186{
187 return 0x00000001;
188}
189static inline u32 ram_in_engine_cs_fg_f(void)
190{
191 return 0x8;
192}
193static inline u32 ram_in_gr_cs_w(void)
194{
195 return 132;
196}
197static inline u32 ram_in_gr_cs_wfi_f(void)
198{
199 return 0x0;
200}
201static inline u32 ram_in_gr_wfi_target_w(void)
202{
203 return 132;
204}
205static inline u32 ram_in_gr_wfi_mode_w(void)
206{
207 return 132;
208}
209static inline u32 ram_in_gr_wfi_mode_physical_v(void)
210{
211 return 0x00000000;
212}
213static inline u32 ram_in_gr_wfi_mode_physical_f(void)
214{
215 return 0x0;
216}
217static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
218{
219 return 0x00000001;
220}
221static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
222{
223 return 0x4;
224}
225static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
226{
227 return (v & 0xfffff) << 12;
228}
229static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
230{
231 return 132;
232}
233static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
234{
235 return (v & 0xff) << 0;
236}
237static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
238{
239 return 133;
240}
241static inline u32 ram_in_base_shift_v(void)
242{
243 return 0x0000000c;
244}
245static inline u32 ram_in_alloc_size_v(void)
246{
247 return 0x00001000;
248}
249static inline u32 ram_fc_size_val_v(void)
250{
251 return 0x00000200;
252}
253static inline u32 ram_fc_gp_put_w(void)
254{
255 return 0;
256}
257static inline u32 ram_fc_userd_w(void)
258{
259 return 2;
260}
261static inline u32 ram_fc_userd_hi_w(void)
262{
263 return 3;
264}
265static inline u32 ram_fc_signature_w(void)
266{
267 return 4;
268}
269static inline u32 ram_fc_gp_get_w(void)
270{
271 return 5;
272}
273static inline u32 ram_fc_pb_get_w(void)
274{
275 return 6;
276}
277static inline u32 ram_fc_pb_get_hi_w(void)
278{
279 return 7;
280}
281static inline u32 ram_fc_pb_top_level_get_w(void)
282{
283 return 8;
284}
285static inline u32 ram_fc_pb_top_level_get_hi_w(void)
286{
287 return 9;
288}
289static inline u32 ram_fc_acquire_w(void)
290{
291 return 12;
292}
293static inline u32 ram_fc_semaphorea_w(void)
294{
295 return 14;
296}
297static inline u32 ram_fc_semaphoreb_w(void)
298{
299 return 15;
300}
301static inline u32 ram_fc_semaphorec_w(void)
302{
303 return 16;
304}
305static inline u32 ram_fc_semaphored_w(void)
306{
307 return 17;
308}
309static inline u32 ram_fc_gp_base_w(void)
310{
311 return 18;
312}
313static inline u32 ram_fc_gp_base_hi_w(void)
314{
315 return 19;
316}
317static inline u32 ram_fc_gp_fetch_w(void)
318{
319 return 20;
320}
321static inline u32 ram_fc_pb_fetch_w(void)
322{
323 return 21;
324}
325static inline u32 ram_fc_pb_fetch_hi_w(void)
326{
327 return 22;
328}
329static inline u32 ram_fc_pb_put_w(void)
330{
331 return 23;
332}
333static inline u32 ram_fc_pb_put_hi_w(void)
334{
335 return 24;
336}
337static inline u32 ram_fc_pb_header_w(void)
338{
339 return 33;
340}
341static inline u32 ram_fc_pb_count_w(void)
342{
343 return 34;
344}
345static inline u32 ram_fc_subdevice_w(void)
346{
347 return 37;
348}
349static inline u32 ram_fc_formats_w(void)
350{
351 return 39;
352}
353static inline u32 ram_fc_allowed_syncpoints_w(void)
354{
355 return 58;
356}
357static inline u32 ram_fc_syncpointa_w(void)
358{
359 return 41;
360}
361static inline u32 ram_fc_syncpointb_w(void)
362{
363 return 42;
364}
365static inline u32 ram_fc_target_w(void)
366{
367 return 43;
368}
369static inline u32 ram_fc_hce_ctrl_w(void)
370{
371 return 57;
372}
373static inline u32 ram_fc_chid_w(void)
374{
375 return 58;
376}
377static inline u32 ram_fc_chid_id_f(u32 v)
378{
379 return (v & 0xfff) << 0;
380}
381static inline u32 ram_fc_chid_id_w(void)
382{
383 return 0;
384}
385static inline u32 ram_fc_config_w(void)
386{
387 return 61;
388}
389static inline u32 ram_fc_runlist_timeslice_w(void)
390{
391 return 62;
392}
393static inline u32 ram_userd_base_shift_v(void)
394{
395 return 0x00000009;
396}
397static inline u32 ram_userd_chan_size_v(void)
398{
399 return 0x00000200;
400}
401static inline u32 ram_userd_put_w(void)
402{
403 return 16;
404}
405static inline u32 ram_userd_get_w(void)
406{
407 return 17;
408}
409static inline u32 ram_userd_ref_w(void)
410{
411 return 18;
412}
413static inline u32 ram_userd_put_hi_w(void)
414{
415 return 19;
416}
417static inline u32 ram_userd_ref_threshold_w(void)
418{
419 return 20;
420}
421static inline u32 ram_userd_top_level_get_w(void)
422{
423 return 22;
424}
425static inline u32 ram_userd_top_level_get_hi_w(void)
426{
427 return 23;
428}
429static inline u32 ram_userd_get_hi_w(void)
430{
431 return 24;
432}
433static inline u32 ram_userd_gp_get_w(void)
434{
435 return 34;
436}
437static inline u32 ram_userd_gp_put_w(void)
438{
439 return 35;
440}
441static inline u32 ram_userd_gp_top_level_get_w(void)
442{
443 return 22;
444}
445static inline u32 ram_userd_gp_top_level_get_hi_w(void)
446{
447 return 23;
448}
449static inline u32 ram_rl_entry_size_v(void)
450{
451 return 0x00000008;
452}
453static inline u32 ram_rl_entry_chid_f(u32 v)
454{
455 return (v & 0xfff) << 0;
456}
457static inline u32 ram_rl_entry_id_f(u32 v)
458{
459 return (v & 0xfff) << 0;
460}
461static inline u32 ram_rl_entry_type_f(u32 v)
462{
463 return (v & 0x1) << 13;
464}
465static inline u32 ram_rl_entry_type_chid_f(void)
466{
467 return 0x0;
468}
469static inline u32 ram_rl_entry_type_tsg_f(void)
470{
471 return 0x2000;
472}
473static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
474{
475 return (v & 0xf) << 14;
476}
477static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
478{
479 return 0xc000;
480}
481static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
482{
483 return (v & 0xff) << 18;
484}
485static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
486{
487 return 0x2000000;
488}
489static inline u32 ram_rl_entry_tsg_length_f(u32 v)
490{
491 return (v & 0x3f) << 26;
492}
493#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h
new file mode 100644
index 00000000..8a587b7c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h
@@ -0,0 +1,409 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_therm_gp10b_h_
51#define _hw_therm_gp10b_h_
52
53static inline u32 therm_use_a_r(void)
54{
55 return 0x00020798;
56}
57static inline u32 therm_use_a_ext_therm_0_enable_f(void)
58{
59 return 0x1;
60}
61static inline u32 therm_use_a_ext_therm_1_enable_f(void)
62{
63 return 0x2;
64}
65static inline u32 therm_use_a_ext_therm_2_enable_f(void)
66{
67 return 0x4;
68}
69static inline u32 therm_evt_ext_therm_0_r(void)
70{
71 return 0x00020700;
72}
73static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
74{
75 return (v & 0x3f) << 24;
76}
77static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
82{
83 return (v & 0x3) << 30;
84}
85static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
86{
87 return 0x00000000;
88}
89static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
90{
91 return 0x00000001;
92}
93static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
94{
95 return 0x00000002;
96}
97static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
98{
99 return 0x00000003;
100}
101static inline u32 therm_evt_ext_therm_1_r(void)
102{
103 return 0x00020704;
104}
105static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
106{
107 return (v & 0x3f) << 24;
108}
109static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
114{
115 return (v & 0x3) << 30;
116}
117static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
118{
119 return 0x00000000;
120}
121static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
122{
123 return 0x00000001;
124}
125static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
126{
127 return 0x00000002;
128}
129static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
130{
131 return 0x00000003;
132}
133static inline u32 therm_evt_ext_therm_2_r(void)
134{
135 return 0x00020708;
136}
137static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
138{
139 return (v & 0x3f) << 24;
140}
141static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
142{
143 return 0x00000003;
144}
145static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
146{
147 return (v & 0x3) << 30;
148}
149static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
150{
151 return 0x00000000;
152}
153static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
154{
155 return 0x00000001;
156}
157static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
158{
159 return 0x00000002;
160}
161static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
162{
163 return 0x00000003;
164}
165static inline u32 therm_weight_1_r(void)
166{
167 return 0x00020024;
168}
169static inline u32 therm_config1_r(void)
170{
171 return 0x00020050;
172}
173static inline u32 therm_config2_r(void)
174{
175 return 0x00020130;
176}
177static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
178{
179 return (v & 0x1) << 24;
180}
181static inline u32 therm_config2_grad_enable_f(u32 v)
182{
183 return (v & 0x1) << 31;
184}
185static inline u32 therm_gate_ctrl_r(u32 i)
186{
187 return 0x00020200 + i*4;
188}
189static inline u32 therm_gate_ctrl_eng_clk_m(void)
190{
191 return 0x3 << 0;
192}
193static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
194{
195 return 0x0;
196}
197static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
198{
199 return 0x1;
200}
201static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
202{
203 return 0x2;
204}
205static inline u32 therm_gate_ctrl_blk_clk_m(void)
206{
207 return 0x3 << 2;
208}
209static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
210{
211 return 0x0;
212}
213static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
214{
215 return 0x4;
216}
217static inline u32 therm_gate_ctrl_eng_pwr_m(void)
218{
219 return 0x3 << 4;
220}
221static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
222{
223 return 0x10;
224}
225static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
226{
227 return 0x00000002;
228}
229static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
230{
231 return 0x20;
232}
233static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
234{
235 return (v & 0x1f) << 8;
236}
237static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
238{
239 return 0x1f << 8;
240}
241static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
242{
243 return (v & 0x7) << 13;
244}
245static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
246{
247 return 0x7 << 13;
248}
249static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
250{
251 return (v & 0xf) << 16;
252}
253static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
254{
255 return 0xf << 16;
256}
257static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
258{
259 return (v & 0xf) << 20;
260}
261static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
262{
263 return 0xf << 20;
264}
265static inline u32 therm_fecs_idle_filter_r(void)
266{
267 return 0x00020288;
268}
269static inline u32 therm_fecs_idle_filter_value_m(void)
270{
271 return 0xffffffff << 0;
272}
273static inline u32 therm_hubmmu_idle_filter_r(void)
274{
275 return 0x0002028c;
276}
277static inline u32 therm_hubmmu_idle_filter_value_m(void)
278{
279 return 0xffffffff << 0;
280}
281static inline u32 therm_clk_slowdown_r(u32 i)
282{
283 return 0x00020160 + i*4;
284}
285static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
286{
287 return (v & 0x3f) << 16;
288}
289static inline u32 therm_clk_slowdown_idle_factor_m(void)
290{
291 return 0x3f << 16;
292}
293static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
294{
295 return (r >> 16) & 0x3f;
296}
297static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
298{
299 return 0x0;
300}
301static inline u32 therm_grad_stepping_table_r(u32 i)
302{
303 return 0x000202c8 + i*4;
304}
305static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
306{
307 return (v & 0x3f) << 0;
308}
309static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
310{
311 return 0x3f << 0;
312}
313static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
314{
315 return 0x1;
316}
317static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
318{
319 return 0x2;
320}
321static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
322{
323 return 0x6;
324}
325static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
326{
327 return 0xe;
328}
329static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
330{
331 return (v & 0x3f) << 6;
332}
333static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
334{
335 return 0x3f << 6;
336}
337static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
338{
339 return (v & 0x3f) << 12;
340}
341static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
342{
343 return 0x3f << 12;
344}
345static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
346{
347 return (v & 0x3f) << 18;
348}
349static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
350{
351 return 0x3f << 18;
352}
353static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
354{
355 return (v & 0x3f) << 24;
356}
357static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
358{
359 return 0x3f << 24;
360}
361static inline u32 therm_grad_stepping0_r(void)
362{
363 return 0x000202c0;
364}
365static inline u32 therm_grad_stepping0_feature_s(void)
366{
367 return 1;
368}
369static inline u32 therm_grad_stepping0_feature_f(u32 v)
370{
371 return (v & 0x1) << 0;
372}
373static inline u32 therm_grad_stepping0_feature_m(void)
374{
375 return 0x1 << 0;
376}
377static inline u32 therm_grad_stepping0_feature_v(u32 r)
378{
379 return (r >> 0) & 0x1;
380}
381static inline u32 therm_grad_stepping0_feature_enable_f(void)
382{
383 return 0x1;
384}
385static inline u32 therm_grad_stepping1_r(void)
386{
387 return 0x000202c4;
388}
389static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
390{
391 return (v & 0x1ffff) << 0;
392}
393static inline u32 therm_clk_timing_r(u32 i)
394{
395 return 0x000203c0 + i*4;
396}
397static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
398{
399 return (v & 0x1) << 16;
400}
401static inline u32 therm_clk_timing_grad_slowdown_m(void)
402{
403 return 0x1 << 16;
404}
405static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
406{
407 return 0x10000;
408}
409#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h
new file mode 100644
index 00000000..df27154f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h
@@ -0,0 +1,109 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_timer_gp10b_h_
51#define _hw_timer_gp10b_h_
52
53static inline u32 timer_pri_timeout_r(void)
54{
55 return 0x00009080;
56}
57static inline u32 timer_pri_timeout_period_f(u32 v)
58{
59 return (v & 0xffffff) << 0;
60}
61static inline u32 timer_pri_timeout_period_m(void)
62{
63 return 0xffffff << 0;
64}
65static inline u32 timer_pri_timeout_period_v(u32 r)
66{
67 return (r >> 0) & 0xffffff;
68}
69static inline u32 timer_pri_timeout_en_f(u32 v)
70{
71 return (v & 0x1) << 31;
72}
73static inline u32 timer_pri_timeout_en_m(void)
74{
75 return 0x1 << 31;
76}
77static inline u32 timer_pri_timeout_en_v(u32 r)
78{
79 return (r >> 31) & 0x1;
80}
81static inline u32 timer_pri_timeout_en_en_enabled_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 timer_pri_timeout_en_en_disabled_f(void)
86{
87 return 0x0;
88}
89static inline u32 timer_pri_timeout_save_0_r(void)
90{
91 return 0x00009084;
92}
93static inline u32 timer_pri_timeout_save_1_r(void)
94{
95 return 0x00009088;
96}
97static inline u32 timer_pri_timeout_fecs_errcode_r(void)
98{
99 return 0x0000908c;
100}
101static inline u32 timer_time_0_r(void)
102{
103 return 0x00009400;
104}
105static inline u32 timer_time_1_r(void)
106{
107 return 0x00009410;
108}
109#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h
new file mode 100644
index 00000000..c6645ca0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h
@@ -0,0 +1,225 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_top_gp10b_h_
51#define _hw_top_gp10b_h_
52
53static inline u32 top_num_gpcs_r(void)
54{
55 return 0x00022430;
56}
57static inline u32 top_num_gpcs_value_v(u32 r)
58{
59 return (r >> 0) & 0x1f;
60}
61static inline u32 top_tpc_per_gpc_r(void)
62{
63 return 0x00022434;
64}
65static inline u32 top_tpc_per_gpc_value_v(u32 r)
66{
67 return (r >> 0) & 0x1f;
68}
69static inline u32 top_num_fbps_r(void)
70{
71 return 0x00022438;
72}
73static inline u32 top_num_fbps_value_v(u32 r)
74{
75 return (r >> 0) & 0x1f;
76}
77static inline u32 top_ltc_per_fbp_r(void)
78{
79 return 0x00022450;
80}
81static inline u32 top_ltc_per_fbp_value_v(u32 r)
82{
83 return (r >> 0) & 0x1f;
84}
85static inline u32 top_slices_per_ltc_r(void)
86{
87 return 0x0002245c;
88}
89static inline u32 top_slices_per_ltc_value_v(u32 r)
90{
91 return (r >> 0) & 0x1f;
92}
93static inline u32 top_num_ltcs_r(void)
94{
95 return 0x00022454;
96}
97static inline u32 top_device_info_r(u32 i)
98{
99 return 0x00022700 + i*4;
100}
101static inline u32 top_device_info__size_1_v(void)
102{
103 return 0x00000040;
104}
105static inline u32 top_device_info_chain_v(u32 r)
106{
107 return (r >> 31) & 0x1;
108}
109static inline u32 top_device_info_chain_enable_v(void)
110{
111 return 0x00000001;
112}
113static inline u32 top_device_info_engine_enum_v(u32 r)
114{
115 return (r >> 26) & 0xf;
116}
117static inline u32 top_device_info_runlist_enum_v(u32 r)
118{
119 return (r >> 21) & 0xf;
120}
121static inline u32 top_device_info_intr_enum_v(u32 r)
122{
123 return (r >> 15) & 0x1f;
124}
125static inline u32 top_device_info_reset_enum_v(u32 r)
126{
127 return (r >> 9) & 0x1f;
128}
129static inline u32 top_device_info_type_enum_v(u32 r)
130{
131 return (r >> 2) & 0x1fffffff;
132}
133static inline u32 top_device_info_type_enum_graphics_v(void)
134{
135 return 0x00000000;
136}
137static inline u32 top_device_info_type_enum_graphics_f(void)
138{
139 return 0x0;
140}
141static inline u32 top_device_info_type_enum_copy2_v(void)
142{
143 return 0x00000003;
144}
145static inline u32 top_device_info_type_enum_copy2_f(void)
146{
147 return 0xc;
148}
149static inline u32 top_device_info_type_enum_lce_v(void)
150{
151 return 0x00000013;
152}
153static inline u32 top_device_info_type_enum_lce_f(void)
154{
155 return 0x4c;
156}
157static inline u32 top_device_info_engine_v(u32 r)
158{
159 return (r >> 5) & 0x1;
160}
161static inline u32 top_device_info_runlist_v(u32 r)
162{
163 return (r >> 4) & 0x1;
164}
165static inline u32 top_device_info_intr_v(u32 r)
166{
167 return (r >> 3) & 0x1;
168}
169static inline u32 top_device_info_reset_v(u32 r)
170{
171 return (r >> 2) & 0x1;
172}
173static inline u32 top_device_info_entry_v(u32 r)
174{
175 return (r >> 0) & 0x3;
176}
177static inline u32 top_device_info_entry_not_valid_v(void)
178{
179 return 0x00000000;
180}
181static inline u32 top_device_info_entry_enum_v(void)
182{
183 return 0x00000002;
184}
185static inline u32 top_device_info_entry_engine_type_v(void)
186{
187 return 0x00000002;
188}
189static inline u32 top_device_info_entry_data_v(void)
190{
191 return 0x00000001;
192}
193static inline u32 top_device_info_data_type_v(u32 r)
194{
195 return (r >> 30) & 0x1;
196}
197static inline u32 top_device_info_data_type_enum2_v(void)
198{
199 return 0x00000000;
200}
201static inline u32 top_device_info_data_inst_id_v(u32 r)
202{
203 return (r >> 26) & 0xf;
204}
205static inline u32 top_device_info_data_pri_base_v(u32 r)
206{
207 return (r >> 12) & 0xfff;
208}
209static inline u32 top_device_info_data_pri_base_align_v(void)
210{
211 return 0x0000000c;
212}
213static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
214{
215 return (r >> 3) & 0x1f;
216}
217static inline u32 top_device_info_data_fault_id_v(u32 r)
218{
219 return (r >> 2) & 0x1;
220}
221static inline u32 top_device_info_data_fault_id_valid_v(void)
222{
223 return 0x00000001;
224}
225#endif
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
new file mode 100644
index 00000000..31c79aff
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
@@ -0,0 +1,225 @@
1/*
2 * GP10B L2
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17
18#include <dt-bindings/memory/tegra-swgroup.h>
19
20#include "gk20a/gk20a.h"
21#include "gm20b/ltc_gm20b.h"
22#include "hw_mc_gp10b.h"
23#include "hw_ltc_gp10b.h"
24
25#include "gk20a/ltc_common.c"
26
27static int gp10b_determine_L2_size_bytes(struct gk20a *g)
28{
29 u32 tmp;
30 int ret;
31
32 gk20a_dbg_fn("");
33
34 tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r());
35
36 ret = g->ltc_count *
37 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp)*1024 *
38 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp);
39
40 gk20a_dbg(gpu_dbg_info, "L2 size: %d\n", ret);
41
42 gk20a_dbg_fn("done");
43
44 return ret;
45}
46
47static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
48{
49 /* max memory size (MB) to cover */
50 u32 max_size = gr->max_comptag_mem;
51 /* one tag line covers 64KB */
52 u32 max_comptag_lines = max_size << 4;
53
54 u32 hw_max_comptag_lines =
55 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v();
56
57 u32 cbc_param =
58 gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
59 u32 comptags_per_cacheline =
60 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param);
61 u32 cacheline_size =
62 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param);
63 u32 slices_per_ltc =
64 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param);
65 u32 cbc_param2 =
66 gk20a_readl(g, ltc_ltcs_ltss_cbc_param2_r());
67 u32 gobs_per_comptagline_per_slice =
68 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(cbc_param2);
69
70 u32 compbit_backing_size;
71
72 int err;
73 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
74
75 gk20a_dbg_fn("");
76
77 if (max_comptag_lines == 0)
78 return 0;
79
80 if (max_comptag_lines > hw_max_comptag_lines)
81 max_comptag_lines = hw_max_comptag_lines;
82
83 compbit_backing_size =
84 roundup(max_comptag_lines * gobs_per_comptagline_per_slice,
85 cacheline_size);
86 compbit_backing_size =
87 roundup(compbit_backing_size * slices_per_ltc * g->ltc_count,
88 g->ops.fb.compressible_page_size(g));
89
90 /* aligned to 2KB * ltc_count */
91 compbit_backing_size +=
92 g->ltc_count << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
93
94 /* must be a multiple of 64KB */
95 compbit_backing_size = roundup(compbit_backing_size, 64*1024);
96
97 gk20a_dbg_info("compbit backing store size : %d",
98 compbit_backing_size);
99 gk20a_dbg_info("max comptag lines : %d",
100 max_comptag_lines);
101 gk20a_dbg_info("gobs_per_comptagline_per_slice: %d",
102 gobs_per_comptagline_per_slice);
103
104 if (platform->is_fmodel)
105 err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
106 else
107 err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size);
108
109 if (err)
110 return err;
111
112 err = gk20a_comptag_allocator_init(&gr->comp_tags, max_comptag_lines);
113 if (err)
114 return err;
115
116 gr->comptags_per_cacheline = comptags_per_cacheline;
117 gr->slices_per_ltc = slices_per_ltc;
118 gr->cacheline_size = cacheline_size;
119 gr->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice;
120
121 return 0;
122}
123
124static void gp10b_ltc_isr(struct gk20a *g)
125{
126 u32 mc_intr, ltc_intr;
127 unsigned int ltc, slice;
128 u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
129 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
130
131 mc_intr = gk20a_readl(g, mc_intr_ltc_r());
132 gk20a_err(dev_from_gk20a(g), "mc_ltc_intr: %08x",
133 mc_intr);
134 for (ltc = 0; ltc < g->ltc_count; ltc++) {
135 if ((mc_intr & 1 << ltc) == 0)
136 continue;
137 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
138 u32 offset = ltc_stride * ltc + lts_stride * slice;
139 ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset);
140
141 /* Detect and handle ECC errors */
142 if (ltc_intr &
143 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) {
144 u32 ecc_stats_reg_val;
145
146 gk20a_err(dev_from_gk20a(g),
147 "Single bit error detected in GPU L2!");
148
149 ecc_stats_reg_val =
150 gk20a_readl(g,
151 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
152 g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] +=
153 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val);
154 ecc_stats_reg_val &=
155 ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m());
156 gk20a_writel(g,
157 ltc_ltc0_lts0_dstg_ecc_report_r() + offset,
158 ecc_stats_reg_val);
159
160 g->ops.mm.l2_flush(g, true);
161 }
162 if (ltc_intr &
163 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) {
164 u32 ecc_stats_reg_val;
165
166 gk20a_err(dev_from_gk20a(g),
167 "Double bit error detected in GPU L2!");
168
169 ecc_stats_reg_val =
170 gk20a_readl(g,
171 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
172 g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] +=
173 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val);
174 ecc_stats_reg_val &=
175 ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m());
176 gk20a_writel(g,
177 ltc_ltc0_lts0_dstg_ecc_report_r() + offset,
178 ecc_stats_reg_val);
179 }
180
181 gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x",
182 ltc, slice, ltc_intr);
183 gk20a_writel(g, ltc_ltc0_lts0_intr_r() +
184 ltc_stride * ltc + lts_stride * slice,
185 ltc_intr);
186 }
187 }
188}
189
190static void gp10b_ltc_init_fs_state(struct gk20a *g)
191{
192 u32 ltc_intr;
193
194 gm20b_ltc_init_fs_state(g);
195
196 gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(),
197 ltc_ltca_g_axi_pctrl_user_sid_f(TEGRA_SID_GPUB));
198
199 /* Enable ECC interrupts */
200 ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
201 ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
202 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f();
203 gk20a_writel(g, ltc_ltcs_ltss_intr_r(),
204 ltc_intr);
205}
206
207void gp10b_init_ltc(struct gpu_ops *gops)
208{
209 gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes;
210 gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry;
211 gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry;
212 gops->ltc.init_cbc = gk20a_ltc_init_cbc;
213
214 /* GM20b specific ops. */
215 gops->ltc.init_fs_state = gp10b_ltc_init_fs_state;
216 gops->ltc.init_comptags = gp10b_ltc_init_comptags;
217 gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl;
218 gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked;
219 gops->ltc.isr = gp10b_ltc_isr;
220 gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config;
221 gops->ltc.flush = gm20b_flush_ltc;
222#ifdef CONFIG_DEBUG_FS
223 gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs;
224#endif
225}
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h
new file mode 100644
index 00000000..7408348e
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef LTC_GP10B_H
15#define LTC_GP10B_H
16struct gpu_ops;
17
18void gp10b_init_ltc(struct gpu_ops *gops);
19#endif
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
new file mode 100644
index 00000000..eda961b6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -0,0 +1,202 @@
1/*
2 * GP20B master
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17
18#include "gk20a/gk20a.h"
19#include "mc_gp10b.h"
20#include "hw_mc_gp10b.h"
21
22void mc_gp10b_intr_enable(struct gk20a *g)
23{
24 u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
25
26 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
27 0xffffffff);
28 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
29 mc_intr_pfifo_pending_f()
30 | mc_intr_replayable_fault_pending_f()
31 | eng_intr_mask;
32 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
33 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
34
35 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
36 0xffffffff);
37 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
38 mc_intr_pfifo_pending_f()
39 | mc_intr_priv_ring_pending_f()
40 | mc_intr_ltc_pending_f()
41 | mc_intr_pbus_pending_f()
42 | eng_intr_mask;
43 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
44 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
45}
46
47void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
48 bool is_stalling, u32 mask)
49{
50 u32 intr_index = 0;
51 u32 reg = 0;
52
53 intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING :
54 NVGPU_MC_INTR_NONSTALLING);
55 if (enable) {
56 reg = mc_intr_en_set_r(intr_index);
57 g->ops.mc.intr_mask_restore[intr_index] |= mask;
58
59 } else {
60 reg = mc_intr_en_clear_r(intr_index);
61 g->ops.mc.intr_mask_restore[intr_index] &= ~mask;
62 }
63
64 gk20a_writel(g, reg, mask);
65}
66
67irqreturn_t mc_gp10b_isr_stall(struct gk20a *g)
68{
69 u32 mc_intr_0;
70
71 if (!g->power_on)
72 return IRQ_NONE;
73
74 /* not from gpu when sharing irq with others */
75 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
76 if (unlikely(!mc_intr_0))
77 return IRQ_NONE;
78
79 gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff);
80
81 return IRQ_WAKE_THREAD;
82}
83
84irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g)
85{
86 u32 mc_intr_1;
87
88 if (!g->power_on)
89 return IRQ_NONE;
90
91 /* not from gpu when sharing irq with others */
92 mc_intr_1 = gk20a_readl(g, mc_intr_r(1));
93 if (unlikely(!mc_intr_1))
94 return IRQ_NONE;
95
96 gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff);
97
98 return IRQ_WAKE_THREAD;
99}
100
101irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
102{
103 u32 mc_intr_0;
104 u32 engine_id_idx;
105 u32 active_engine_id = 0;
106 u32 engine_enum = ENGINE_INVAL_GK20A;
107
108 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
109
110 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
111
112 gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
113
114 for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
115 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
116
117 if (mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) {
118 engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
119 /* GR Engine */
120 if (engine_enum == ENGINE_GR_GK20A) {
121 gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
122 }
123
124 /* CE Engine */
125 if (((engine_enum == ENGINE_GRCE_GK20A) ||
126 (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
127 g->ops.ce2.isr_stall){
128 g->ops.ce2.isr_stall(g,
129 g->fifo.engine_info[active_engine_id].inst_id,
130 g->fifo.engine_info[active_engine_id].pri_base);
131 }
132 }
133 }
134 if (mc_intr_0 & mc_intr_pfifo_pending_f())
135 gk20a_fifo_isr(g);
136 if (mc_intr_0 & mc_intr_pmu_pending_f())
137 gk20a_pmu_isr(g);
138 if (mc_intr_0 & mc_intr_priv_ring_pending_f())
139 gk20a_priv_ring_isr(g);
140 if (mc_intr_0 & mc_intr_ltc_pending_f())
141 g->ops.ltc.isr(g);
142 if (mc_intr_0 & mc_intr_pbus_pending_f())
143 gk20a_pbus_isr(g);
144
145 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
146 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
147
148 return IRQ_HANDLED;
149}
150
151irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
152{
153 u32 mc_intr_1;
154 u32 engine_id_idx;
155 u32 active_engine_id = 0;
156 u32 engine_enum = ENGINE_INVAL_GK20A;
157
158 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
159
160 mc_intr_1 = gk20a_readl(g, mc_intr_r(1));
161
162 gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1);
163
164 if (mc_intr_1 & mc_intr_pfifo_pending_f())
165 gk20a_fifo_nonstall_isr(g);
166
167 for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
168 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
169
170 if (mc_intr_1 & g->fifo.engine_info[active_engine_id].intr_mask) {
171 engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
172 /* GR Engine */
173 if (engine_enum == ENGINE_GR_GK20A) {
174 gk20a_gr_nonstall_isr(g);
175 }
176
177 /* CE Engine */
178 if (((engine_enum == ENGINE_GRCE_GK20A) ||
179 (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
180 g->ops.ce2.isr_nonstall) {
181 g->ops.ce2.isr_nonstall(g,
182 g->fifo.engine_info[active_engine_id].inst_id,
183 g->fifo.engine_info[active_engine_id].pri_base);
184 }
185 }
186 }
187
188 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
189 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
190
191 return IRQ_HANDLED;
192}
193
194void gp10b_init_mc(struct gpu_ops *gops)
195{
196 gops->mc.intr_enable = mc_gp10b_intr_enable;
197 gops->mc.intr_unit_config = mc_gp10b_intr_unit_config;
198 gops->mc.isr_stall = mc_gp10b_isr_stall;
199 gops->mc.isr_nonstall = mc_gp10b_isr_nonstall;
200 gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall;
201 gops->mc.isr_thread_nonstall = mc_gp10b_intr_thread_nonstall;
202}
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
new file mode 100644
index 00000000..b2ec4be4
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef MC_GP20B_H
15#define MC_GP20B_H
16struct gk20a;
17
18enum MC_INTERRUPT_REGLIST {
19 NVGPU_MC_INTR_STALLING = 0,
20 NVGPU_MC_INTR_NONSTALLING,
21};
22
23void gp10b_init_mc(struct gpu_ops *gops);
24void mc_gp10b_intr_enable(struct gk20a *g);
25void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
26 bool is_stalling, u32 mask);
27irqreturn_t mc_gp10b_isr_stall(struct gk20a *g);
28irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g);
29irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g);
30irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g);
31#endif
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
new file mode 100644
index 00000000..1b6b6641
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -0,0 +1,417 @@
1/*
2 * GP10B MMU
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/pm_runtime.h>
17#include <linux/dma-mapping.h>
18#include "gk20a/gk20a.h"
19#include "mm_gp10b.h"
20#include "rpfb_gp10b.h"
21#include "hw_fb_gp10b.h"
22#include "hw_ram_gp10b.h"
23#include "hw_bus_gp10b.h"
24#include "hw_gmmu_gp10b.h"
25#include "gk20a/semaphore_gk20a.h"
26
27static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g)
28{
29 return 36;
30}
31
32static int gp10b_init_mm_setup_hw(struct gk20a *g)
33{
34 struct mm_gk20a *mm = &g->mm;
35 struct mem_desc *inst_block = &mm->bar1.inst_block;
36 int err = 0;
37
38 gk20a_dbg_fn("");
39
40 g->ops.fb.set_mmu_page_size(g);
41
42 gk20a_writel(g, fb_niso_flush_sysmem_addr_r(),
43 (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0)
44 >> 8ULL));
45
46 g->ops.mm.bar1_bind(g, inst_block);
47
48 if (g->ops.mm.init_bar2_mm_hw_setup) {
49 err = g->ops.mm.init_bar2_mm_hw_setup(g);
50 if (err)
51 return err;
52 }
53
54 if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g))
55 return -EBUSY;
56
57 err = gp10b_replayable_pagefault_buffer_init(g);
58
59 gk20a_dbg_fn("done");
60 return err;
61
62}
63
64static int gb10b_init_bar2_vm(struct gk20a *g)
65{
66 int err;
67 struct mm_gk20a *mm = &g->mm;
68 struct vm_gk20a *vm = &mm->bar2.vm;
69 struct mem_desc *inst_block = &mm->bar2.inst_block;
70 u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size;
71
72 /* BAR2 aperture size is 32MB */
73 mm->bar2.aperture_size = 32 << 20;
74 gk20a_dbg_info("bar2 vm size = 0x%x", mm->bar2.aperture_size);
75 gk20a_init_vm(mm, vm, big_page_size, SZ_4K,
76 mm->bar2.aperture_size - SZ_4K,
77 mm->bar2.aperture_size, false, false, "bar2");
78
79 /* allocate instance mem for bar2 */
80 err = gk20a_alloc_inst_block(g, inst_block);
81 if (err)
82 goto clean_up_va;
83
84 g->ops.mm.init_inst_block(inst_block, vm, big_page_size);
85
86 return 0;
87
88clean_up_va:
89 gk20a_deinit_vm(vm);
90 return err;
91}
92
93
94static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g)
95{
96 struct mm_gk20a *mm = &g->mm;
97 struct mem_desc *inst_block = &mm->bar2.inst_block;
98 u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block);
99
100 gk20a_dbg_fn("");
101
102 g->ops.fb.set_mmu_page_size(g);
103
104 inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v());
105 gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa);
106
107 gk20a_writel(g, bus_bar2_block_r(),
108 gk20a_aperture_mask(g, inst_block,
109 bus_bar2_block_target_sys_mem_ncoh_f(),
110 bus_bar2_block_target_vid_mem_f()) |
111 bus_bar2_block_mode_virtual_f() |
112 bus_bar2_block_ptr_f(inst_pa));
113
114 gk20a_dbg_fn("done");
115 return 0;
116}
117
118static u64 gp10b_mm_phys_addr_translate(struct gk20a *g, u64 phys_addr,
119 u32 flags)
120{
121 if (!device_is_iommuable(dev_from_gk20a(g)))
122 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT)
123 return phys_addr |
124 1ULL << NVGPU_MM_GET_IO_COHERENCE_BIT;
125
126 return phys_addr;
127}
128
129static u64 gp10b_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl,
130 u32 flags)
131{
132 if (!device_is_iommuable(dev_from_gk20a(g)))
133 return gp10b_mm_phys_addr_translate(g, sg_phys(sgl), flags);
134
135 if (sg_dma_address(sgl) == 0)
136 return gp10b_mm_phys_addr_translate(g, sg_phys(sgl), flags);
137
138 if (sg_dma_address(sgl) == DMA_ERROR_CODE)
139 return 0;
140
141 return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl));
142}
143
144static u32 pde3_from_index(u32 i)
145{
146 return i * gmmu_new_pde__size_v() / sizeof(u32);
147}
148
149static u32 pte3_from_index(u32 i)
150{
151 return i * gmmu_new_pte__size_v() / sizeof(u32);
152}
153
154static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
155 struct gk20a_mm_entry *parent,
156 u32 i, u32 gmmu_pgsz_idx,
157 struct scatterlist **sgl,
158 u64 *offset,
159 u64 *iova,
160 u32 kind_v, u64 *ctag,
161 bool cacheable, bool unmapped_pte,
162 int rw_flag, bool sparse, bool priv,
163 enum gk20a_aperture aperture)
164{
165 struct gk20a *g = gk20a_from_vm(vm);
166 u64 pte_addr = 0;
167 struct gk20a_mm_entry *pte = parent->entries + i;
168 u32 pde_v[2] = {0, 0};
169 u32 pde;
170
171 gk20a_dbg_fn("");
172
173 pte_addr = gk20a_pde_addr(g, pte) >> gmmu_new_pde_address_shift_v();
174
175 pde_v[0] |= gk20a_aperture_mask(g, &pte->mem,
176 gmmu_new_pde_aperture_sys_mem_ncoh_f(),
177 gmmu_new_pde_aperture_video_memory_f());
178 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
179 pde_v[0] |= gmmu_new_pde_vol_true_f();
180 pde_v[1] |= pte_addr >> 24;
181 pde = pde3_from_index(i);
182
183 gk20a_pde_wr32(g, parent, pde + 0, pde_v[0]);
184 gk20a_pde_wr32(g, parent, pde + 1, pde_v[1]);
185
186 gk20a_dbg(gpu_dbg_pte, "pde:%d,sz=%d = 0x%x,0x%08x",
187 i, gmmu_pgsz_idx, pde_v[1], pde_v[0]);
188 gk20a_dbg_fn("done");
189 return 0;
190}
191
192static u32 pde0_from_index(u32 i)
193{
194 return i * gmmu_new_dual_pde__size_v() / sizeof(u32);
195}
196
197static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
198 struct gk20a_mm_entry *pte,
199 u32 i, u32 gmmu_pgsz_idx,
200 struct scatterlist **sgl,
201 u64 *offset,
202 u64 *iova,
203 u32 kind_v, u64 *ctag,
204 bool cacheable, bool unmapped_pte,
205 int rw_flag, bool sparse, bool priv,
206 enum gk20a_aperture aperture)
207{
208 struct gk20a *g = gk20a_from_vm(vm);
209 bool small_valid, big_valid;
210 u32 pte_addr_small = 0, pte_addr_big = 0;
211 struct gk20a_mm_entry *entry = pte->entries + i;
212 u32 pde_v[4] = {0, 0, 0, 0};
213 u32 pde;
214
215 gk20a_dbg_fn("");
216
217 small_valid = entry->mem.size && entry->pgsz == gmmu_page_size_small;
218 big_valid = entry->mem.size && entry->pgsz == gmmu_page_size_big;
219
220 if (small_valid) {
221 pte_addr_small = gk20a_pde_addr(g, entry)
222 >> gmmu_new_dual_pde_address_shift_v();
223 }
224
225 if (big_valid)
226 pte_addr_big = gk20a_pde_addr(g, entry)
227 >> gmmu_new_dual_pde_address_big_shift_v();
228
229 if (small_valid) {
230 pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small);
231 pde_v[2] |= gk20a_aperture_mask(g, &entry->mem,
232 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(),
233 gmmu_new_dual_pde_aperture_small_video_memory_f());
234 pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f();
235 pde_v[3] |= pte_addr_small >> 24;
236 }
237
238 if (big_valid) {
239 pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big);
240 pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f();
241 pde_v[0] |= gk20a_aperture_mask(g, &entry->mem,
242 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(),
243 gmmu_new_dual_pde_aperture_big_video_memory_f());
244 pde_v[1] |= pte_addr_big >> 28;
245 }
246
247 pde = pde0_from_index(i);
248
249 gk20a_pde_wr32(g, pte, pde + 0, pde_v[0]);
250 gk20a_pde_wr32(g, pte, pde + 1, pde_v[1]);
251 gk20a_pde_wr32(g, pte, pde + 2, pde_v[2]);
252 gk20a_pde_wr32(g, pte, pde + 3, pde_v[3]);
253
254 gk20a_dbg(gpu_dbg_pte, "pde:%d,sz=%d [0x%08x, 0x%08x, 0x%x, 0x%08x]",
255 i, gmmu_pgsz_idx, pde_v[3], pde_v[2], pde_v[1], pde_v[0]);
256 gk20a_dbg_fn("done");
257 return 0;
258}
259
260static int update_gmmu_pte_locked(struct vm_gk20a *vm,
261 struct gk20a_mm_entry *pte,
262 u32 i, u32 gmmu_pgsz_idx,
263 struct scatterlist **sgl,
264 u64 *offset,
265 u64 *iova,
266 u32 kind_v, u64 *ctag,
267 bool cacheable, bool unmapped_pte,
268 int rw_flag, bool sparse, bool priv,
269 enum gk20a_aperture aperture)
270{
271 struct gk20a *g = vm->mm->g;
272 u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx];
273 u64 ctag_granularity = g->ops.fb.compression_page_size(g);
274 u32 pte_w[2] = {0, 0}; /* invalid pte */
275 u32 pte_i;
276
277 if (*iova) {
278 u32 pte_valid = unmapped_pte ?
279 gmmu_new_pte_valid_false_f() :
280 gmmu_new_pte_valid_true_f();
281 u32 iova_v = *iova >> gmmu_new_pte_address_shift_v();
282 u32 pte_addr = aperture == APERTURE_SYSMEM ?
283 gmmu_new_pte_address_sys_f(iova_v) :
284 gmmu_new_pte_address_vid_f(iova_v);
285 u32 pte_tgt = __gk20a_aperture_mask(g, aperture,
286 gmmu_new_pte_aperture_sys_mem_ncoh_f(),
287 gmmu_new_pte_aperture_video_memory_f());
288
289 pte_w[0] = pte_valid | pte_addr | pte_tgt;
290
291 if (priv)
292 pte_w[0] |= gmmu_new_pte_privilege_true_f();
293
294 pte_w[1] = *iova >> (24 + gmmu_new_pte_address_shift_v()) |
295 gmmu_new_pte_kind_f(kind_v) |
296 gmmu_new_pte_comptagline_f((u32)(*ctag / ctag_granularity));
297
298 if (rw_flag == gk20a_mem_flag_read_only)
299 pte_w[0] |= gmmu_new_pte_read_only_true_f();
300 if (unmapped_pte && !cacheable)
301 pte_w[0] |= gmmu_new_pte_read_only_true_f();
302 else if (!cacheable)
303 pte_w[0] |= gmmu_new_pte_vol_true_f();
304
305 gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d"
306 " ctag=%d vol=%d"
307 " [0x%08x, 0x%08x]",
308 i, *iova,
309 kind_v, (u32)(*ctag / ctag_granularity), !cacheable,
310 pte_w[1], pte_w[0]);
311
312 if (*ctag)
313 *ctag += page_size;
314 } else if (sparse) {
315 pte_w[0] = gmmu_new_pte_valid_false_f();
316 pte_w[0] |= gmmu_new_pte_vol_true_f();
317 } else {
318 gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i);
319 }
320
321 pte_i = pte3_from_index(i);
322
323 gk20a_pde_wr32(g, pte, pte_i + 0, pte_w[0]);
324 gk20a_pde_wr32(g, pte, pte_i + 1, pte_w[1]);
325
326 if (*iova) {
327 *iova += page_size;
328 *offset += page_size;
329 if (*sgl && *offset + page_size > (*sgl)->length) {
330 u64 new_iova;
331 *sgl = sg_next(*sgl);
332 if (*sgl) {
333 new_iova = sg_phys(*sgl);
334 gk20a_dbg(gpu_dbg_pte, "chunk address %llx, size %d",
335 new_iova, (*sgl)->length);
336 if (new_iova) {
337 *offset = 0;
338 *iova = new_iova;
339 }
340 }
341 }
342 }
343 return 0;
344}
345
346static const struct gk20a_mmu_level gp10b_mm_levels[] = {
347 {.hi_bit = {48, 48},
348 .lo_bit = {47, 47},
349 .update_entry = update_gmmu_pde3_locked,
350 .entry_size = 8},
351 {.hi_bit = {46, 46},
352 .lo_bit = {38, 38},
353 .update_entry = update_gmmu_pde3_locked,
354 .entry_size = 8},
355 {.hi_bit = {37, 37},
356 .lo_bit = {29, 29},
357 .update_entry = update_gmmu_pde3_locked,
358 .entry_size = 8},
359 {.hi_bit = {28, 28},
360 .lo_bit = {21, 21},
361 .update_entry = update_gmmu_pde0_locked,
362 .entry_size = 16},
363 {.hi_bit = {20, 20},
364 .lo_bit = {12, 16},
365 .update_entry = update_gmmu_pte_locked,
366 .entry_size = 8},
367 {.update_entry = NULL}
368};
369
370static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g,
371 u32 big_page_size)
372{
373 return gp10b_mm_levels;
374}
375
376static void gp10b_mm_init_pdb(struct gk20a *g, struct mem_desc *inst_block,
377 struct vm_gk20a *vm)
378{
379 u64 pdb_addr = gk20a_mem_get_base_addr(g, &vm->pdb.mem, 0);
380 u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
381 u32 pdb_addr_hi = u64_hi32(pdb_addr);
382
383 gk20a_dbg_info("pde pa=0x%llx", pdb_addr);
384
385 gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_lo_w(),
386 gk20a_aperture_mask(g, &vm->pdb.mem,
387 ram_in_page_dir_base_target_sys_mem_ncoh_f(),
388 ram_in_page_dir_base_target_vid_mem_f()) |
389 ram_in_page_dir_base_vol_true_f() |
390 ram_in_page_dir_base_lo_f(pdb_addr_lo) |
391 1 << 10);
392
393 gk20a_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
394 ram_in_page_dir_base_hi_f(pdb_addr_hi));
395}
396
397static void gp10b_remove_bar2_vm(struct gk20a *g)
398{
399 struct mm_gk20a *mm = &g->mm;
400
401 gp10b_replayable_pagefault_buffer_deinit(g);
402 gk20a_remove_vm(&mm->bar2.vm, &mm->bar2.inst_block);
403}
404
405
406void gp10b_init_mm(struct gpu_ops *gops)
407{
408 gm20b_init_mm(gops);
409 gops->mm.get_physical_addr_bits = gp10b_mm_get_physical_addr_bits;
410 gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw;
411 gops->mm.init_bar2_vm = gb10b_init_bar2_vm;
412 gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup;
413 gops->mm.get_iova_addr = gp10b_mm_iova_addr;
414 gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels;
415 gops->mm.init_pdb = gp10b_mm_init_pdb;
416 gops->mm.remove_bar2_vm = gp10b_remove_bar2_vm;
417}
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
new file mode 100644
index 00000000..034944e0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef MM_GP10B_H
15#define MM_GP10B_H
16
17#define NVGPU_MM_GET_IO_COHERENCE_BIT 35
18
19struct gpu_ops;
20
21void gp10b_init_mm(struct gpu_ops *gops);
22#endif
diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c
new file mode 100644
index 00000000..8cf6d5e8
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c
@@ -0,0 +1,751 @@
1/*
2 * GP10B Tegra Platform Interface
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/of_platform.h>
17#include <linux/nvhost.h>
18#include <linux/debugfs.h>
19#include <linux/tegra-powergate.h>
20#include <linux/platform_data/tegra_edp.h>
21#include <uapi/linux/nvgpu.h>
22#include <linux/dma-buf.h>
23#include <linux/nvmap.h>
24#include <linux/reset.h>
25#include <soc/tegra/tegra_bpmp.h>
26#include <linux/hashtable.h>
27#include "gk20a/platform_gk20a.h"
28#include "gk20a/gk20a.h"
29#include "gk20a/gk20a_scale.h"
30#include "platform_tegra.h"
31#include "gr_gp10b.h"
32#include "ltc_gp10b.h"
33#include "hw_gr_gp10b.h"
34#include "hw_ltc_gp10b.h"
35#include "gp10b_sysfs.h"
36#include <linux/platform/tegra/emc_bwmgr.h>
37
38#define GP10B_MAX_SUPPORTED_FREQS 11
39static unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS];
40
41#define TEGRA_GP10B_BW_PER_FREQ 64
42#define TEGRA_DDR4_BW_PER_FREQ 16
43
44#define EMC_BW_RATIO (TEGRA_GP10B_BW_PER_FREQ / TEGRA_DDR4_BW_PER_FREQ)
45
46static struct {
47 char *name;
48 unsigned long default_rate;
49} tegra_gp10b_clocks[] = {
50 {"gpu", 1000000000},
51 {"gpu_sys", 204000000} };
52
53static void gr_gp10b_remove_sysfs(struct device *dev);
54
55/*
56 * gp10b_tegra_get_clocks()
57 *
58 * This function finds clocks in tegra platform and populates
59 * the clock information to gp10b platform data.
60 */
61
62static int gp10b_tegra_get_clocks(struct device *dev)
63{
64 struct gk20a_platform *platform = dev_get_drvdata(dev);
65 unsigned int i;
66
67 if (platform->is_fmodel)
68 return 0;
69
70 platform->num_clks = 0;
71 for (i = 0; i < ARRAY_SIZE(tegra_gp10b_clocks); i++) {
72 long rate = tegra_gp10b_clocks[i].default_rate;
73 struct clk *c;
74
75 c = clk_get(dev, tegra_gp10b_clocks[i].name);
76 if (IS_ERR(c)) {
77 gk20a_err(dev, "cannot get clock %s",
78 tegra_gp10b_clocks[i].name);
79 } else {
80 clk_set_rate(c, rate);
81 platform->clk[i] = c;
82 }
83 }
84 platform->num_clks = i;
85
86 return 0;
87}
88
89static void gp10b_tegra_scale_init(struct device *dev)
90{
91 struct gk20a_platform *platform = gk20a_get_platform(dev);
92 struct gk20a_scale_profile *profile = platform->g->scale_profile;
93 struct tegra_bwmgr_client *bwmgr_handle;
94
95 if (!profile)
96 return;
97
98 bwmgr_handle = tegra_bwmgr_register(TEGRA_BWMGR_CLIENT_GPU);
99 if (!bwmgr_handle)
100 return;
101
102 profile->private_data = (void *)bwmgr_handle;
103}
104
105static void gp10b_tegra_scale_exit(struct device *dev)
106{
107 struct gk20a_platform *platform = gk20a_get_platform(dev);
108 struct gk20a_scale_profile *profile = platform->g->scale_profile;
109
110 if (profile)
111 tegra_bwmgr_unregister(
112 (struct tegra_bwmgr_client *)profile->private_data);
113}
114
115static int gp10b_tegra_probe(struct device *dev)
116{
117 struct gk20a_platform *platform = dev_get_drvdata(dev);
118 struct device_node *np = dev->of_node;
119 struct device_node *host1x_node;
120 struct platform_device *host1x_pdev;
121 const __be32 *host1x_ptr;
122
123 host1x_ptr = of_get_property(np, "nvidia,host1x", NULL);
124 if (!host1x_ptr) {
125 gk20a_err(dev, "host1x device not available");
126 return -ENOSYS;
127 }
128
129 host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr));
130 host1x_pdev = of_find_device_by_node(host1x_node);
131 if (!host1x_pdev) {
132 gk20a_err(dev, "host1x device not available");
133 return -ENOSYS;
134 }
135
136 platform->g->host1x_dev = host1x_pdev;
137 platform->bypass_smmu = !device_is_iommuable(dev);
138 platform->disable_bigpage = platform->bypass_smmu;
139
140 platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
141 = false;
142 platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
143 = false;
144
145 platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false;
146 platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false;
147
148 platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_gfxp =
149 debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR,
150 platform->debugfs,
151 &platform->g->gr.t18x.ctx_vars.force_preemption_gfxp);
152
153 platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_cilp =
154 debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR,
155 platform->debugfs,
156 &platform->g->gr.t18x.ctx_vars.force_preemption_cilp);
157
158 platform->g->gr.t18x.ctx_vars.debugfs_dump_ctxsw_stats =
159 debugfs_create_bool("dump_ctxsw_stats_on_channel_close",
160 S_IRUGO|S_IWUSR,
161 platform->debugfs,
162 &platform->g->gr.t18x.
163 ctx_vars.dump_ctxsw_stats_on_channel_close);
164
165 platform->g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem;
166
167 gp10b_tegra_get_clocks(dev);
168
169 return 0;
170}
171
172static int gp10b_tegra_late_probe(struct device *dev)
173{
174 /*Create GP10B specific sysfs*/
175 gp10b_create_sysfs(dev);
176
177 /* Initialise tegra specific scaling quirks */
178 gp10b_tegra_scale_init(dev);
179 return 0;
180}
181
182static int gp10b_tegra_remove(struct device *dev)
183{
184 gr_gp10b_remove_sysfs(dev);
185 /*Remove GP10B specific sysfs*/
186 gp10b_remove_sysfs(dev);
187
188 /* deinitialise tegra specific scaling quirks */
189 gp10b_tegra_scale_exit(dev);
190
191 return 0;
192
193}
194
195static bool gp10b_tegra_is_railgated(struct device *dev)
196{
197 bool ret = false;
198
199 if (tegra_bpmp_running())
200 ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU);
201
202 return ret;
203}
204
205static int gp10b_tegra_railgate(struct device *dev)
206{
207 struct gk20a_platform *platform = gk20a_get_platform(dev);
208 struct gk20a_scale_profile *profile = platform->g->scale_profile;
209
210 /* remove emc frequency floor */
211 if (profile)
212 tegra_bwmgr_set_emc(
213 (struct tegra_bwmgr_client *)profile->private_data,
214 0, TEGRA_BWMGR_SET_EMC_FLOOR);
215
216 if (tegra_bpmp_running() &&
217 tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) {
218 int i;
219 for (i = 0; i < platform->num_clks; i++) {
220 if (platform->clk[i])
221 clk_disable_unprepare(platform->clk[i]);
222 }
223 tegra_powergate_partition(TEGRA_POWERGATE_GPU);
224 }
225 return 0;
226}
227
228static int gp10b_tegra_unrailgate(struct device *dev)
229{
230 int ret = 0;
231 struct gk20a_platform *platform = gk20a_get_platform(dev);
232 struct gk20a_scale_profile *profile = platform->g->scale_profile;
233
234 if (tegra_bpmp_running()) {
235 int i;
236 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU);
237 for (i = 0; i < platform->num_clks; i++) {
238 if (platform->clk[i])
239 clk_prepare_enable(platform->clk[i]);
240 }
241 }
242
243 /* to start with set emc frequency floor to max rate*/
244 if (profile)
245 tegra_bwmgr_set_emc(
246 (struct tegra_bwmgr_client *)profile->private_data,
247 tegra_bwmgr_get_max_emc_rate(),
248 TEGRA_BWMGR_SET_EMC_FLOOR);
249 return ret;
250}
251
252static int gp10b_tegra_suspend(struct device *dev)
253{
254 return 0;
255}
256
257static int gp10b_tegra_reset_assert(struct device *dev)
258{
259 struct gk20a_platform *platform = gk20a_get_platform(dev);
260 int ret = 0;
261
262 if (!platform->reset_control)
263 return -EINVAL;
264
265 ret = reset_control_assert(platform->reset_control);
266
267 return ret;
268}
269
270static int gp10b_tegra_reset_deassert(struct device *dev)
271{
272 struct gk20a_platform *platform = gk20a_get_platform(dev);
273 int ret = 0;
274
275 if (!platform->reset_control)
276 return -EINVAL;
277
278 ret = reset_control_deassert(platform->reset_control);
279
280 return ret;
281}
282
283static void gp10b_tegra_prescale(struct device *dev)
284{
285 struct gk20a *g = get_gk20a(dev);
286 u32 avg = 0;
287
288 gk20a_dbg_fn("");
289
290 gk20a_pmu_load_norm(g, &avg);
291
292 gk20a_dbg_fn("done");
293}
294
295static void gp10b_tegra_postscale(struct device *pdev,
296 unsigned long freq)
297{
298 struct gk20a_platform *platform = gk20a_get_platform(pdev);
299 struct gk20a_scale_profile *profile = platform->g->scale_profile;
300 struct gk20a *g = get_gk20a(pdev);
301 unsigned long emc_rate;
302
303 gk20a_dbg_fn("");
304 if (profile && !gp10b_tegra_is_railgated(pdev)) {
305 emc_rate = (freq * EMC_BW_RATIO * g->emc3d_ratio) / 1000;
306
307 if (emc_rate > tegra_bwmgr_get_max_emc_rate())
308 emc_rate = tegra_bwmgr_get_max_emc_rate();
309
310 tegra_bwmgr_set_emc(
311 (struct tegra_bwmgr_client *)profile->private_data,
312 emc_rate, TEGRA_BWMGR_SET_EMC_FLOOR);
313 }
314 gk20a_dbg_fn("done");
315}
316
317static unsigned long gp10b_get_clk_rate(struct device *dev)
318{
319 struct gk20a_platform *platform = gk20a_get_platform(dev);
320
321 return clk_get_rate(platform->clk[0]);
322
323}
324
325static long gp10b_round_clk_rate(struct device *dev, unsigned long rate)
326{
327 struct gk20a_platform *platform = gk20a_get_platform(dev);
328
329 return clk_round_rate(platform->clk[0], rate);
330}
331
332static int gp10b_set_clk_rate(struct device *dev, unsigned long rate)
333{
334 struct gk20a_platform *platform = gk20a_get_platform(dev);
335
336 return clk_set_rate(platform->clk[0], rate);
337}
338
339static int gp10b_clk_get_freqs(struct device *dev,
340 unsigned long **freqs, int *num_freqs)
341{
342 struct gk20a_platform *platform = gk20a_get_platform(dev);
343 unsigned long min_rate, max_rate, freq_step, rate;
344 int i;
345
346 min_rate = clk_round_rate(platform->clk[0], 0);
347 max_rate = clk_round_rate(platform->clk[0], (UINT_MAX - 1));
348 freq_step = (max_rate - min_rate)/(GP10B_MAX_SUPPORTED_FREQS - 1);
349 gk20a_dbg_info("min rate: %ld max rate: %ld freq step %ld\n",
350 min_rate, max_rate, freq_step);
351
352 for (i = 0; i < GP10B_MAX_SUPPORTED_FREQS; i++) {
353 rate = min_rate + i * freq_step;
354 gp10b_freq_table[i] = clk_round_rate(platform->clk[0], rate);
355 }
356 /* Fill freq table */
357 *freqs = gp10b_freq_table;
358 *num_freqs = GP10B_MAX_SUPPORTED_FREQS;
359 return 0;
360}
361
362struct gk20a_platform t18x_gpu_tegra_platform = {
363 .has_syncpoints = true,
364
365 /* power management configuration */
366 .railgate_delay = 500,
367
368 /* power management configuration */
369 .can_railgate = true,
370 .enable_elpg = true,
371 .can_elpg = true,
372 .enable_blcg = true,
373 .enable_slcg = true,
374 .enable_elcg = true,
375 .enable_aelpg = true,
376
377 /* ptimer src frequency in hz*/
378 .ptimer_src_freq = 31250000,
379
380 .ch_wdt_timeout_ms = 5000,
381
382 .probe = gp10b_tegra_probe,
383 .late_probe = gp10b_tegra_late_probe,
384 .remove = gp10b_tegra_remove,
385
386 /* power management callbacks */
387 .suspend = gp10b_tegra_suspend,
388 .railgate = gp10b_tegra_railgate,
389 .unrailgate = gp10b_tegra_unrailgate,
390 .is_railgated = gp10b_tegra_is_railgated,
391
392 .busy = gk20a_tegra_busy,
393 .idle = gk20a_tegra_idle,
394
395 .dump_platform_dependencies = gk20a_tegra_debug_dump,
396
397 .default_big_page_size = SZ_64K,
398
399 .has_cde = true,
400
401 .has_ce = true,
402
403 .clk_get_rate = gp10b_get_clk_rate,
404 .clk_round_rate = gp10b_round_clk_rate,
405 .clk_set_rate = gp10b_set_clk_rate,
406 .get_clk_freqs = gp10b_clk_get_freqs,
407
408 /* frequency scaling configuration */
409 .prescale = gp10b_tegra_prescale,
410 .postscale = gp10b_tegra_postscale,
411 .devfreq_governor = "nvhost_podgov",
412
413 .qos_notify = gk20a_scale_qos_notify,
414
415 .secure_alloc = gk20a_tegra_secure_alloc,
416 .secure_page_alloc = gk20a_tegra_secure_page_alloc,
417
418 .reset_assert = gp10b_tegra_reset_assert,
419 .reset_deassert = gp10b_tegra_reset_deassert,
420
421 .force_reset_in_do_idle = false,
422
423 .soc_name = "tegra18x",
424
425 .vidmem_is_vidmem = false,
426};
427
428
429#define ECC_STAT_NAME_MAX_SIZE 100
430
431
432static DEFINE_HASHTABLE(ecc_hash_table, 5);
433
434static struct device_attribute *dev_attr_sm_lrf_ecc_single_err_count_array;
435static struct device_attribute *dev_attr_sm_lrf_ecc_double_err_count_array;
436
437static struct device_attribute *dev_attr_sm_shm_ecc_sec_count_array;
438static struct device_attribute *dev_attr_sm_shm_ecc_sed_count_array;
439static struct device_attribute *dev_attr_sm_shm_ecc_ded_count_array;
440
441static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe0_count_array;
442static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe0_count_array;
443static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe0_count_array;
444static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe0_count_array;
445static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe1_count_array;
446static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe1_count_array;
447static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe1_count_array;
448static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe1_count_array;
449
450static struct device_attribute *dev_attr_l2_ecc_sec_count_array;
451static struct device_attribute *dev_attr_l2_ecc_ded_count_array;
452
453
454static u32 gen_ecc_hash_key(char *str)
455{
456 int i = 0;
457 u32 hash_key = 0;
458
459 while (str[i]) {
460 hash_key += (u32)(str[i]);
461 i++;
462 };
463
464 return hash_key;
465}
466
467static ssize_t ecc_stat_show(struct device *dev,
468 struct device_attribute *attr,
469 char *buf)
470{
471 const char *ecc_stat_full_name = attr->attr.name;
472 const char *ecc_stat_base_name;
473 unsigned int hw_unit;
474 struct ecc_stat *ecc_stat;
475 u32 hash_key;
476
477 if (sscanf(ecc_stat_full_name, "ltc%u", &hw_unit) == 1) {
478 ecc_stat_base_name = &(ecc_stat_full_name[strlen("ltc0_")]);
479 } else if (sscanf(ecc_stat_full_name, "gpc0_tpc%u", &hw_unit) == 1) {
480 ecc_stat_base_name = &(ecc_stat_full_name[strlen("gpc0_tpc0_")]);
481 } else {
482 return snprintf(buf,
483 PAGE_SIZE,
484 "Error: Invalid ECC stat name!\n");
485 }
486
487 hash_key = gen_ecc_hash_key((char *)ecc_stat_base_name);
488 hash_for_each_possible(ecc_hash_table,
489 ecc_stat,
490 hash_node,
491 hash_key) {
492 if (!strcmp(ecc_stat_full_name, ecc_stat->names[hw_unit]))
493 return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stat->counters[hw_unit]);
494 }
495
496 return snprintf(buf, PAGE_SIZE, "Error: No ECC stat found!\n");
497}
498
499static int ecc_stat_create(struct device *dev,
500 int is_l2,
501 char *ecc_stat_name,
502 struct ecc_stat *ecc_stat,
503 struct device_attribute *dev_attr_array)
504{
505 int error = 0;
506 struct gk20a *g = get_gk20a(dev);
507 int num_hw_units = 0;
508 int hw_unit = 0;
509 u32 hash_key = 0;
510
511 if (is_l2)
512 num_hw_units = g->ltc_count;
513 else
514 num_hw_units = g->gr.tpc_count;
515
516 /* Allocate arrays */
517 dev_attr_array = kzalloc(sizeof(struct device_attribute) * num_hw_units, GFP_KERNEL);
518 ecc_stat->counters = kzalloc(sizeof(u32) * num_hw_units, GFP_KERNEL);
519 ecc_stat->names = kzalloc(sizeof(char *) * num_hw_units, GFP_KERNEL);
520 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
521 ecc_stat->names[hw_unit] = kzalloc(sizeof(char) * ECC_STAT_NAME_MAX_SIZE, GFP_KERNEL);
522 }
523
524 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
525 /* Fill in struct device_attribute members */
526 if (is_l2)
527 snprintf(ecc_stat->names[hw_unit],
528 ECC_STAT_NAME_MAX_SIZE,
529 "ltc%d_%s",
530 hw_unit,
531 ecc_stat_name);
532 else
533 snprintf(ecc_stat->names[hw_unit],
534 ECC_STAT_NAME_MAX_SIZE,
535 "gpc0_tpc%d_%s",
536 hw_unit,
537 ecc_stat_name);
538
539 sysfs_attr_init(&dev_attr_array[hw_unit].attr);
540 dev_attr_array[hw_unit].attr.name = ecc_stat->names[hw_unit];
541 dev_attr_array[hw_unit].attr.mode = VERIFY_OCTAL_PERMISSIONS(S_IRUGO);
542 dev_attr_array[hw_unit].show = ecc_stat_show;
543 dev_attr_array[hw_unit].store = NULL;
544
545 /* Create sysfs file */
546 error |= device_create_file(dev, &dev_attr_array[hw_unit]);
547 }
548
549 /* Add hash table entry */
550 hash_key = gen_ecc_hash_key(ecc_stat_name);
551 hash_add(ecc_hash_table,
552 &ecc_stat->hash_node,
553 hash_key);
554
555 return error;
556}
557
558static void ecc_stat_remove(struct device *dev,
559 int is_l2,
560 struct ecc_stat *ecc_stat,
561 struct device_attribute *dev_attr_array)
562{
563 struct gk20a *g = get_gk20a(dev);
564 int num_hw_units = 0;
565 int hw_unit = 0;
566
567 if (is_l2)
568 num_hw_units = g->ltc_count;
569 else
570 num_hw_units = g->gr.tpc_count;
571
572 /* Remove sysfs files */
573 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
574 device_remove_file(dev, &dev_attr_array[hw_unit]);
575 }
576
577 /* Remove hash table entry */
578 hash_del(&ecc_stat->hash_node);
579
580 /* Free arrays */
581 kfree(ecc_stat->counters);
582 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
583 kfree(ecc_stat->names[hw_unit]);
584 }
585 kfree(ecc_stat->names);
586 kfree(dev_attr_array);
587}
588
589void gr_gp10b_create_sysfs(struct device *dev)
590{
591 int error = 0;
592 struct gk20a *g = get_gk20a(dev);
593
594 /* This stat creation function is called on GR init. GR can get
595 initialized multiple times but we only need to create the ECC
596 stats once. Therefore, add the following check to avoid
597 creating duplicate stat sysfs nodes. */
598 if (g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters != NULL)
599 return;
600
601 error |= ecc_stat_create(dev,
602 0,
603 "sm_lrf_ecc_single_err_count",
604 &g->gr.t18x.ecc_stats.sm_lrf_single_err_count,
605 dev_attr_sm_lrf_ecc_single_err_count_array);
606 error |= ecc_stat_create(dev,
607 0,
608 "sm_lrf_ecc_double_err_count",
609 &g->gr.t18x.ecc_stats.sm_lrf_double_err_count,
610 dev_attr_sm_lrf_ecc_double_err_count_array);
611
612 error |= ecc_stat_create(dev,
613 0,
614 "sm_shm_ecc_sec_count",
615 &g->gr.t18x.ecc_stats.sm_shm_sec_count,
616 dev_attr_sm_shm_ecc_sec_count_array);
617 error |= ecc_stat_create(dev,
618 0,
619 "sm_shm_ecc_sed_count",
620 &g->gr.t18x.ecc_stats.sm_shm_sed_count,
621 dev_attr_sm_shm_ecc_sed_count_array);
622 error |= ecc_stat_create(dev,
623 0,
624 "sm_shm_ecc_ded_count",
625 &g->gr.t18x.ecc_stats.sm_shm_ded_count,
626 dev_attr_sm_shm_ecc_ded_count_array);
627
628 error |= ecc_stat_create(dev,
629 0,
630 "tex_ecc_total_sec_pipe0_count",
631 &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count,
632 dev_attr_tex_ecc_total_sec_pipe0_count_array);
633 error |= ecc_stat_create(dev,
634 0,
635 "tex_ecc_total_ded_pipe0_count",
636 &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count,
637 dev_attr_tex_ecc_total_ded_pipe0_count_array);
638 error |= ecc_stat_create(dev,
639 0,
640 "tex_ecc_unique_sec_pipe0_count",
641 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count,
642 dev_attr_tex_ecc_unique_sec_pipe0_count_array);
643 error |= ecc_stat_create(dev,
644 0,
645 "tex_ecc_unique_ded_pipe0_count",
646 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count,
647 dev_attr_tex_ecc_unique_ded_pipe0_count_array);
648 error |= ecc_stat_create(dev,
649 0,
650 "tex_ecc_total_sec_pipe1_count",
651 &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count,
652 dev_attr_tex_ecc_total_sec_pipe1_count_array);
653 error |= ecc_stat_create(dev,
654 0,
655 "tex_ecc_total_ded_pipe1_count",
656 &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count,
657 dev_attr_tex_ecc_total_ded_pipe1_count_array);
658 error |= ecc_stat_create(dev,
659 0,
660 "tex_ecc_unique_sec_pipe1_count",
661 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count,
662 dev_attr_tex_ecc_unique_sec_pipe1_count_array);
663 error |= ecc_stat_create(dev,
664 0,
665 "tex_ecc_unique_ded_pipe1_count",
666 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count,
667 dev_attr_tex_ecc_unique_ded_pipe1_count_array);
668
669 error |= ecc_stat_create(dev,
670 1,
671 "lts0_ecc_sec_count",
672 &g->gr.t18x.ecc_stats.l2_sec_count,
673 dev_attr_l2_ecc_sec_count_array);
674 error |= ecc_stat_create(dev,
675 1,
676 "lts0_ecc_ded_count",
677 &g->gr.t18x.ecc_stats.l2_ded_count,
678 dev_attr_l2_ecc_ded_count_array);
679
680 if (error)
681 dev_err(dev, "Failed to create sysfs attributes!\n");
682}
683
684static void gr_gp10b_remove_sysfs(struct device *dev)
685{
686 struct gk20a *g = get_gk20a(dev);
687
688 ecc_stat_remove(dev,
689 0,
690 &g->gr.t18x.ecc_stats.sm_lrf_single_err_count,
691 dev_attr_sm_lrf_ecc_single_err_count_array);
692 ecc_stat_remove(dev,
693 0,
694 &g->gr.t18x.ecc_stats.sm_lrf_double_err_count,
695 dev_attr_sm_lrf_ecc_double_err_count_array);
696
697 ecc_stat_remove(dev,
698 0,
699 &g->gr.t18x.ecc_stats.sm_shm_sec_count,
700 dev_attr_sm_shm_ecc_sec_count_array);
701 ecc_stat_remove(dev,
702 0,
703 &g->gr.t18x.ecc_stats.sm_shm_sed_count,
704 dev_attr_sm_shm_ecc_sed_count_array);
705 ecc_stat_remove(dev,
706 0,
707 &g->gr.t18x.ecc_stats.sm_shm_ded_count,
708 dev_attr_sm_shm_ecc_ded_count_array);
709
710 ecc_stat_remove(dev,
711 0,
712 &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count,
713 dev_attr_tex_ecc_total_sec_pipe0_count_array);
714 ecc_stat_remove(dev,
715 0,
716 &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count,
717 dev_attr_tex_ecc_total_ded_pipe0_count_array);
718 ecc_stat_remove(dev,
719 0,
720 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count,
721 dev_attr_tex_ecc_unique_sec_pipe0_count_array);
722 ecc_stat_remove(dev,
723 0,
724 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count,
725 dev_attr_tex_ecc_unique_ded_pipe0_count_array);
726 ecc_stat_remove(dev,
727 0,
728 &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count,
729 dev_attr_tex_ecc_total_sec_pipe1_count_array);
730 ecc_stat_remove(dev,
731 0,
732 &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count,
733 dev_attr_tex_ecc_total_ded_pipe1_count_array);
734 ecc_stat_remove(dev,
735 0,
736 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count,
737 dev_attr_tex_ecc_unique_sec_pipe1_count_array);
738 ecc_stat_remove(dev,
739 0,
740 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count,
741 dev_attr_tex_ecc_unique_ded_pipe1_count_array);
742
743 ecc_stat_remove(dev,
744 1,
745 &g->gr.t18x.ecc_stats.l2_sec_count,
746 dev_attr_l2_ecc_sec_count_array);
747 ecc_stat_remove(dev,
748 1,
749 &g->gr.t18x.ecc_stats.l2_ded_count,
750 dev_attr_l2_ecc_ded_count_array);
751}
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
new file mode 100644
index 00000000..12337934
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
@@ -0,0 +1,493 @@
1/*
2 * GP10B PMU
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/delay.h> /* for udelay */
17#include <linux/tegra-fuse.h>
18#include "gk20a/gk20a.h"
19#include "gk20a/pmu_gk20a.h"
20#include "gm20b/acr_gm20b.h"
21#include "gm20b/pmu_gm20b.h"
22
23#include "pmu_gp10b.h"
24#include "hw_pwr_gp10b.h"
25#include "hw_fuse_gp10b.h"
26#include "gp10b_sysfs.h"
27
28#define gp10b_dbg_pmu(fmt, arg...) \
29 gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
30/*!
31 * Structure/object which single register write need to be done during PG init
32 * sequence to set PROD values.
33 */
34struct pg_init_sequence_list {
35 u32 regaddr;
36 u32 writeval;
37};
38
39/* PROD settings for ELPG sequencing registers*/
40static struct pg_init_sequence_list _pginitseq_gp10b[] = {
41 {0x0010ab10, 0x0000868B} ,
42 {0x0010e118, 0x8590848F} ,
43 {0x0010e000, 0} ,
44 {0x0010e06c, 0x000000A3} ,
45 {0x0010e06c, 0x000000A0} ,
46 {0x0010e06c, 0x00000095} ,
47 {0x0010e06c, 0x000000A6} ,
48 {0x0010e06c, 0x0000008C} ,
49 {0x0010e06c, 0x00000080} ,
50 {0x0010e06c, 0x00000081} ,
51 {0x0010e06c, 0x00000087} ,
52 {0x0010e06c, 0x00000088} ,
53 {0x0010e06c, 0x0000008D} ,
54 {0x0010e06c, 0x00000082} ,
55 {0x0010e06c, 0x00000083} ,
56 {0x0010e06c, 0x00000089} ,
57 {0x0010e06c, 0x0000008A} ,
58 {0x0010e06c, 0x000000A2} ,
59 {0x0010e06c, 0x00000097} ,
60 {0x0010e06c, 0x00000092} ,
61 {0x0010e06c, 0x00000099} ,
62 {0x0010e06c, 0x0000009B} ,
63 {0x0010e06c, 0x0000009D} ,
64 {0x0010e06c, 0x0000009F} ,
65 {0x0010e06c, 0x000000A1} ,
66 {0x0010e06c, 0x00000096} ,
67 {0x0010e06c, 0x00000091} ,
68 {0x0010e06c, 0x00000098} ,
69 {0x0010e06c, 0x0000009A} ,
70 {0x0010e06c, 0x0000009C} ,
71 {0x0010e06c, 0x0000009E} ,
72 {0x0010ab14, 0x00000000} ,
73 {0x0010e024, 0x00000000} ,
74 {0x0010e028, 0x00000000} ,
75 {0x0010e11c, 0x00000000} ,
76 {0x0010ab1c, 0x140B0BFF} ,
77 {0x0010e020, 0x0E2626FF} ,
78 {0x0010e124, 0x251010FF} ,
79 {0x0010ab20, 0x89abcdef} ,
80 {0x0010ab24, 0x00000000} ,
81 {0x0010e02c, 0x89abcdef} ,
82 {0x0010e030, 0x00000000} ,
83 {0x0010e128, 0x89abcdef} ,
84 {0x0010e12c, 0x00000000} ,
85 {0x0010ab28, 0x7FFFFFFF} ,
86 {0x0010ab2c, 0x70000000} ,
87 {0x0010e034, 0x7FFFFFFF} ,
88 {0x0010e038, 0x70000000} ,
89 {0x0010e130, 0x7FFFFFFF} ,
90 {0x0010e134, 0x70000000} ,
91 {0x0010ab30, 0x00000000} ,
92 {0x0010ab34, 0x00000001} ,
93 {0x00020004, 0x00000000} ,
94 {0x0010e138, 0x00000000} ,
95 {0x0010e040, 0x00000000} ,
96 {0x0010e168, 0x00000000} ,
97 {0x0010e114, 0x0000A5A4} ,
98 {0x0010e110, 0x00000000} ,
99 {0x0010e10c, 0x8590848F} ,
100 {0x0010e05c, 0x00000000} ,
101 {0x0010e044, 0x00000000} ,
102 {0x0010a644, 0x0000868B} ,
103 {0x0010a648, 0x00000000} ,
104 {0x0010a64c, 0x00829493} ,
105 {0x0010a650, 0x00000000} ,
106 {0x0010e000, 0} ,
107 {0x0010e068, 0x000000A3} ,
108 {0x0010e068, 0x000000A0} ,
109 {0x0010e068, 0x00000095} ,
110 {0x0010e068, 0x000000A6} ,
111 {0x0010e068, 0x0000008C} ,
112 {0x0010e068, 0x00000080} ,
113 {0x0010e068, 0x00000081} ,
114 {0x0010e068, 0x00000087} ,
115 {0x0010e068, 0x00000088} ,
116 {0x0010e068, 0x0000008D} ,
117 {0x0010e068, 0x00000082} ,
118 {0x0010e068, 0x00000083} ,
119 {0x0010e068, 0x00000089} ,
120 {0x0010e068, 0x0000008A} ,
121 {0x0010e068, 0x000000A2} ,
122 {0x0010e068, 0x00000097} ,
123 {0x0010e068, 0x00000092} ,
124 {0x0010e068, 0x00000099} ,
125 {0x0010e068, 0x0000009B} ,
126 {0x0010e068, 0x0000009D} ,
127 {0x0010e068, 0x0000009F} ,
128 {0x0010e068, 0x000000A1} ,
129 {0x0010e068, 0x00000096} ,
130 {0x0010e068, 0x00000091} ,
131 {0x0010e068, 0x00000098} ,
132 {0x0010e068, 0x0000009A} ,
133 {0x0010e068, 0x0000009C} ,
134 {0x0010e068, 0x0000009E} ,
135 {0x0010e000, 0} ,
136 {0x0010e004, 0x0000008E},
137};
138
139static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
140 u32 flags)
141{
142 struct pmu_gk20a *pmu = &g->pmu;
143 struct pmu_cmd cmd;
144 u32 seq;
145
146 gk20a_dbg_fn("");
147
148 gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone);
149 if (g->ops.pmu.lspmuwprinitdone) {
150 /* send message to load FECS falcon */
151 memset(&cmd, 0, sizeof(struct pmu_cmd));
152 cmd.hdr.unit_id = PMU_UNIT_ACR;
153 cmd.hdr.size = PMU_CMD_HDR_SIZE +
154 sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons);
155 cmd.cmd.acr.boot_falcons.cmd_type =
156 PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS;
157 cmd.cmd.acr.boot_falcons.flags = flags;
158 cmd.cmd.acr.boot_falcons.falconidmask =
159 falconidmask;
160 cmd.cmd.acr.boot_falcons.usevamask = 0;
161 cmd.cmd.acr.boot_falcons.wprvirtualbase.lo =
162 u64_lo32(g->pmu.wpr_buf.gpu_va);
163 cmd.cmd.acr.boot_falcons.wprvirtualbase.hi =
164 u64_hi32(g->pmu.wpr_buf.gpu_va);
165 gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
166 falconidmask);
167 gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
168 pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
169 }
170
171 gk20a_dbg_fn("done");
172 return;
173}
174
175int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
176{
177 u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
178
179 /* GM20B PMU supports loading FECS and GPCCS only */
180 if (falconidmask == 0)
181 return -EINVAL;
182 if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) |
183 (1 << LSF_FALCON_ID_GPCCS)))
184 return -EINVAL;
185 g->ops.pmu.lsfloadedfalconid = 0;
186 /* check whether pmu is ready to bootstrap lsf if not wait for it */
187 if (!g->ops.pmu.lspmuwprinitdone) {
188 pmu_wait_message_cond(&g->pmu,
189 gk20a_get_gr_idle_timeout(g),
190 &g->ops.pmu.lspmuwprinitdone, 1);
191 /* check again if it still not ready indicate an error */
192 if (!g->ops.pmu.lspmuwprinitdone) {
193 gk20a_err(dev_from_gk20a(g),
194 "PMU not ready to load LSF");
195 return -ETIMEDOUT;
196 }
197 }
198 /* load falcon(s) */
199 gp10b_pmu_load_multiple_falcons(g, falconidmask, flags);
200 pmu_wait_message_cond(&g->pmu,
201 gk20a_get_gr_idle_timeout(g),
202 &g->ops.pmu.lsfloadedfalconid, falconidmask);
203 if (g->ops.pmu.lsfloadedfalconid != falconidmask)
204 return -ETIMEDOUT;
205 return 0;
206}
207
208static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg,
209 void *param, u32 handle, u32 status)
210{
211 gk20a_dbg_fn("");
212
213 if (status != 0) {
214 gk20a_err(dev_from_gk20a(g), "GR PARAM cmd aborted");
215 /* TBD: disable ELPG */
216 return;
217 }
218
219 gp10b_dbg_pmu("GR PARAM is acknowledged from PMU %x \n",
220 msg->msg.pg.msg_type);
221
222 return;
223}
224
225int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
226{
227 struct pmu_gk20a *pmu = &g->pmu;
228 struct pmu_cmd cmd;
229 u32 seq;
230
231 if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) {
232 memset(&cmd, 0, sizeof(struct pmu_cmd));
233 cmd.hdr.unit_id = PMU_UNIT_PG;
234 cmd.hdr.size = PMU_CMD_HDR_SIZE +
235 sizeof(struct pmu_pg_cmd_gr_init_param);
236 cmd.cmd.pg.gr_init_param.cmd_type =
237 PMU_PG_CMD_ID_PG_PARAM;
238 cmd.cmd.pg.gr_init_param.sub_cmd_id =
239 PMU_PG_PARAM_CMD_GR_INIT_PARAM;
240 cmd.cmd.pg.gr_init_param.featuremask =
241 PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
242
243 gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM ");
244 gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
245 pmu_handle_gr_param_msg, pmu, &seq, ~0);
246
247 } else
248 return -EINVAL;
249
250 return 0;
251}
252
253void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
254 u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt)
255{
256 struct pmu_gk20a *pmu = &g->pmu;
257 struct pmu_pg_stats_v1 stats;
258
259 pmu_copy_from_dmem(pmu,
260 pmu->stat_dmem_offset[pg_engine_id],
261 (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0);
262
263 *ingating_time = stats.total_sleep_timeus;
264 *ungating_time = stats.total_nonsleep_timeus;
265 *gating_cnt = stats.entry_count;
266}
267
268static int gp10b_pmu_setup_elpg(struct gk20a *g)
269{
270 int ret = 0;
271 u32 reg_writes;
272 u32 index;
273
274 gk20a_dbg_fn("");
275
276 if (g->elpg_enabled) {
277 reg_writes = ((sizeof(_pginitseq_gp10b) /
278 sizeof((_pginitseq_gp10b)[0])));
279 /* Initialize registers with production values*/
280 for (index = 0; index < reg_writes; index++) {
281 gk20a_writel(g, _pginitseq_gp10b[index].regaddr,
282 _pginitseq_gp10b[index].writeval);
283 }
284 }
285
286 gk20a_dbg_fn("done");
287 return ret;
288}
289
290void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
291{
292 gk20a_writel(g, pwr_falcon_dmatrfbase_r(),
293 addr);
294 gk20a_writel(g, pwr_falcon_dmatrfbase1_r(),
295 0x0);
296}
297
298static int gp10b_init_pmu_setup_hw1(struct gk20a *g)
299{
300 struct pmu_gk20a *pmu = &g->pmu;
301 int err;
302
303 gk20a_dbg_fn("");
304
305 mutex_lock(&pmu->isr_mutex);
306 pmu_reset(pmu);
307 pmu->isr_enabled = true;
308 mutex_unlock(&pmu->isr_mutex);
309
310 /* setup apertures - virtual */
311 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
312 pwr_fbif_transcfg_mem_type_virtual_f());
313 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
314 pwr_fbif_transcfg_mem_type_virtual_f());
315
316 /* setup apertures - physical */
317 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
318 pwr_fbif_transcfg_mem_type_physical_f() |
319 pwr_fbif_transcfg_target_local_fb_f());
320 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
321 pwr_fbif_transcfg_mem_type_physical_f() |
322 pwr_fbif_transcfg_target_coherent_sysmem_f());
323 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
324 pwr_fbif_transcfg_mem_type_physical_f() |
325 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
326
327 err = pmu_bootstrap(pmu);
328 if (err)
329 return err;
330
331 gk20a_dbg_fn("done");
332 return 0;
333
334}
335
336static void pmu_handle_ecc_en_dis_msg(struct gk20a *g, struct pmu_msg *msg,
337 void *param, u32 handle, u32 status)
338{
339 struct pmu_gk20a *pmu = &g->pmu;
340 struct pmu_msg_lrf_tex_ltc_dram_en_dis *ecc =
341 &msg->msg.lrf_tex_ltc_dram.en_dis;
342 gk20a_dbg_fn("");
343
344 if (status != 0) {
345 gk20a_err(dev_from_gk20a(g), "ECC en dis cmd aborted");
346 return;
347 }
348 if (msg->msg.lrf_tex_ltc_dram.msg_type !=
349 PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS) {
350 gk20a_err(dev_from_gk20a(g),
351 "Invalid msg for LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS cmd");
352 return;
353 } else if (ecc->pmu_status != 0) {
354 gk20a_err(dev_from_gk20a(g),
355 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg status = %x",
356 ecc->pmu_status);
357 gk20a_err(dev_from_gk20a(g),
358 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg en fail = %x",
359 ecc->en_fail_mask);
360 gk20a_err(dev_from_gk20a(g),
361 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg dis fail = %x",
362 ecc->dis_fail_mask);
363 } else
364 pmu->override_done = 1;
365 gk20a_dbg_fn("done");
366}
367
368static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask)
369{
370 struct pmu_gk20a *pmu = &g->pmu;
371 struct pmu_cmd cmd;
372 u32 seq;
373 int status;
374 u32 val;
375 gk20a_dbg_fn("");
376
377 tegra_fuse_readl(FUSE_OPT_ECC_EN, &val);
378 if (!val) {
379 gk20a_err(dev_from_gk20a(g), "Board not ECC capable");
380 return -1;
381 }
382 if (!(g->acr.capabilities &
383 ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE)) {
384 gk20a_err(dev_from_gk20a(g), "check ACR capabilities");
385 return -1;
386 }
387 memset(&cmd, 0, sizeof(struct pmu_cmd));
388 cmd.hdr.unit_id = PMU_UNIT_FECS_MEM_OVERRIDE;
389 cmd.hdr.size = PMU_CMD_HDR_SIZE +
390 sizeof(struct pmu_cmd_lrf_tex_ltc_dram_en_dis);
391 cmd.cmd.lrf_tex_ltc_dram.en_dis.cmd_type =
392 PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS;
393 cmd.cmd.lrf_tex_ltc_dram.en_dis.en_dis_mask = (u8)(bitmask & 0xff);
394
395 gp10b_dbg_pmu("cmd post PMU_ECC_CMD_ID_EN_DIS_ECC");
396 pmu->override_done = 0;
397 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
398 pmu_handle_ecc_en_dis_msg, NULL, &seq, ~0);
399 if (status)
400 gk20a_err(dev_from_gk20a(g), "ECC override failed");
401 else
402 pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g),
403 &pmu->override_done, 1);
404 gk20a_dbg_fn("done");
405 return status;
406}
407
408static bool gp10b_is_lazy_bootstrap(u32 falcon_id)
409{
410 bool enable_status = false;
411
412 switch (falcon_id) {
413 case LSF_FALCON_ID_FECS:
414 enable_status = false;
415 break;
416 case LSF_FALCON_ID_GPCCS:
417 enable_status = true;
418 break;
419 default:
420 break;
421 }
422
423 return enable_status;
424}
425
426static bool gp10b_is_priv_load(u32 falcon_id)
427{
428 bool enable_status = false;
429
430 switch (falcon_id) {
431 case LSF_FALCON_ID_FECS:
432 enable_status = false;
433 break;
434 case LSF_FALCON_ID_GPCCS:
435 enable_status = true;
436 break;
437 default:
438 break;
439 }
440
441 return enable_status;
442}
443
444/*Dump Security related fuses*/
445static void pmu_dump_security_fuses_gp10b(struct gk20a *g)
446{
447 u32 val;
448
449 gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x",
450 gk20a_readl(g, fuse_opt_sec_debug_en_r()));
451 gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
452 gk20a_readl(g, fuse_opt_priv_sec_en_r()));
453 tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val);
454 gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
455 val);
456}
457
458static bool gp10b_is_pmu_supported(struct gk20a *g)
459{
460 return true;
461}
462
463void gp10b_init_pmu_ops(struct gpu_ops *gops)
464{
465 gops->pmu.is_pmu_supported = gp10b_is_pmu_supported;
466 if (gops->privsecurity) {
467 gm20b_init_secure_pmu(gops);
468 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
469 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
470 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
471 gops->pmu.is_priv_load = gp10b_is_priv_load;
472 } else {
473 gk20a_init_pmu_ops(gops);
474 gops->pmu.load_lsfalcon_ucode = NULL;
475 gops->pmu.init_wpr_region = NULL;
476 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
477 }
478 gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg;
479 gops->pmu.lspmuwprinitdone = false;
480 gops->pmu.fecsbootstrapdone = false;
481 gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase;
482 gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics;
483 gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init;
484 gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list;
485 gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list;
486 gops->pmu.pmu_lpwr_enable_pg = NULL;
487 gops->pmu.pmu_lpwr_disable_pg = NULL;
488 gops->pmu.pmu_pg_param_post_init = NULL;
489 gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd =
490 send_ecc_overide_en_dis_cmd;
491 gops->pmu.reset = gk20a_pmu_reset;
492 gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gp10b;
493}
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
new file mode 100644
index 00000000..c9ac9d41
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
@@ -0,0 +1,26 @@
1/*
2 * GP10B PMU
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef __PMU_GP10B_H_
17#define __PMU_GP10B_H_
18
19void gp10b_init_pmu_ops(struct gpu_ops *gops);
20int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
21int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
22void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr);
23void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
24 u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt);
25
26#endif /*__PMU_GP10B_H_*/
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
new file mode 100644
index 00000000..a494c9b8
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
@@ -0,0 +1,511 @@
1/*
2 * Tegra GK20A GPU Debugger Driver Register Ops
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/bsearch.h>
22#include <uapi/linux/nvgpu.h>
23
24#include "gk20a/gk20a.h"
25#include "gk20a/dbg_gpu_gk20a.h"
26#include "gk20a/regops_gk20a.h"
27#include "regops_gp10b.h"
28
29static const struct regop_offset_range gp10b_global_whitelist_ranges[] = {
30 { 0x000004f0, 1},
31 { 0x00001a00, 3},
32 { 0x00002800, 128},
33 { 0x00009400, 1},
34 { 0x00009410, 1},
35 { 0x00009480, 1},
36 { 0x00020200, 24},
37 { 0x00021c00, 4},
38 { 0x00021c14, 3},
39 { 0x00021c24, 1},
40 { 0x00021c2c, 69},
41 { 0x00021d44, 1},
42 { 0x00021d4c, 1},
43 { 0x00021d54, 1},
44 { 0x00021d5c, 1},
45 { 0x00021d64, 2},
46 { 0x00021d70, 16},
47 { 0x00022430, 7},
48 { 0x00022450, 1},
49 { 0x0002245c, 1},
50 { 0x00070000, 5},
51 { 0x000884e0, 1},
52 { 0x0008e00c, 1},
53 { 0x00100c18, 3},
54 { 0x00100c84, 1},
55 { 0x00104038, 1},
56 { 0x0010a0a8, 1},
57 { 0x0010a4f0, 1},
58 { 0x0010e490, 1},
59 { 0x0013cc14, 1},
60 { 0x00140028, 1},
61 { 0x00140280, 1},
62 { 0x001402a0, 1},
63 { 0x00140350, 1},
64 { 0x00140480, 1},
65 { 0x001404a0, 1},
66 { 0x00140550, 1},
67 { 0x00142028, 1},
68 { 0x00142280, 1},
69 { 0x001422a0, 1},
70 { 0x00142350, 1},
71 { 0x00142480, 1},
72 { 0x001424a0, 1},
73 { 0x00142550, 1},
74 { 0x0017e028, 1},
75 { 0x0017e280, 1},
76 { 0x0017e294, 1},
77 { 0x0017e29c, 2},
78 { 0x0017e2ac, 1},
79 { 0x0017e350, 1},
80 { 0x0017e39c, 1},
81 { 0x0017e480, 1},
82 { 0x0017e4a0, 1},
83 { 0x0017e550, 1},
84 { 0x00180040, 41},
85 { 0x001800ec, 10},
86 { 0x00180240, 41},
87 { 0x001802ec, 10},
88 { 0x00180440, 41},
89 { 0x001804ec, 10},
90 { 0x00180640, 41},
91 { 0x001806ec, 10},
92 { 0x00180840, 41},
93 { 0x001808ec, 10},
94 { 0x00180a40, 41},
95 { 0x00180aec, 10},
96 { 0x00180c40, 41},
97 { 0x00180cec, 10},
98 { 0x00180e40, 41},
99 { 0x00180eec, 10},
100 { 0x001a0040, 41},
101 { 0x001a00ec, 10},
102 { 0x001a0240, 41},
103 { 0x001a02ec, 10},
104 { 0x001a0440, 41},
105 { 0x001a04ec, 10},
106 { 0x001a0640, 41},
107 { 0x001a06ec, 10},
108 { 0x001a0840, 41},
109 { 0x001a08ec, 10},
110 { 0x001a0a40, 41},
111 { 0x001a0aec, 10},
112 { 0x001a0c40, 41},
113 { 0x001a0cec, 10},
114 { 0x001a0e40, 41},
115 { 0x001a0eec, 10},
116 { 0x001b0040, 41},
117 { 0x001b00ec, 10},
118 { 0x001b0240, 41},
119 { 0x001b02ec, 10},
120 { 0x001b0440, 41},
121 { 0x001b04ec, 10},
122 { 0x001b0640, 41},
123 { 0x001b06ec, 10},
124 { 0x001b0840, 41},
125 { 0x001b08ec, 10},
126 { 0x001b0a40, 41},
127 { 0x001b0aec, 10},
128 { 0x001b0c40, 41},
129 { 0x001b0cec, 10},
130 { 0x001b0e40, 41},
131 { 0x001b0eec, 10},
132 { 0x001b4000, 1},
133 { 0x001b4008, 1},
134 { 0x001b4010, 3},
135 { 0x001b4020, 3},
136 { 0x001b4030, 3},
137 { 0x001b4040, 3},
138 { 0x001b4050, 3},
139 { 0x001b4060, 4},
140 { 0x001b4074, 7},
141 { 0x001b4094, 3},
142 { 0x001b40a4, 1},
143 { 0x001b4100, 6},
144 { 0x001b4124, 2},
145 { 0x001b8000, 1},
146 { 0x001b8008, 1},
147 { 0x001b8010, 3},
148 { 0x001bc000, 1},
149 { 0x001bc008, 1},
150 { 0x001bc010, 3},
151 { 0x001be000, 1},
152 { 0x001be008, 1},
153 { 0x001be010, 3},
154 { 0x00400500, 1},
155 { 0x0040415c, 1},
156 { 0x00404468, 1},
157 { 0x00404498, 1},
158 { 0x00405800, 1},
159 { 0x00405840, 2},
160 { 0x00405850, 1},
161 { 0x00405908, 1},
162 { 0x00405b40, 1},
163 { 0x00405b50, 1},
164 { 0x00406024, 5},
165 { 0x00407010, 1},
166 { 0x00407808, 1},
167 { 0x0040803c, 1},
168 { 0x00408804, 1},
169 { 0x0040880c, 1},
170 { 0x00408900, 2},
171 { 0x00408910, 1},
172 { 0x00408944, 1},
173 { 0x00408984, 1},
174 { 0x004090a8, 1},
175 { 0x004098a0, 1},
176 { 0x00409b00, 1},
177 { 0x0041000c, 1},
178 { 0x00410110, 1},
179 { 0x00410184, 1},
180 { 0x0041040c, 1},
181 { 0x00410510, 1},
182 { 0x00410584, 1},
183 { 0x00418000, 1},
184 { 0x00418008, 1},
185 { 0x00418380, 2},
186 { 0x00418400, 2},
187 { 0x004184a0, 1},
188 { 0x00418604, 1},
189 { 0x00418680, 1},
190 { 0x00418704, 1},
191 { 0x00418714, 1},
192 { 0x00418800, 1},
193 { 0x0041881c, 1},
194 { 0x00418830, 1},
195 { 0x00418884, 1},
196 { 0x004188b0, 1},
197 { 0x004188c8, 3},
198 { 0x004188fc, 1},
199 { 0x00418b04, 1},
200 { 0x00418c04, 1},
201 { 0x00418c10, 8},
202 { 0x00418c88, 1},
203 { 0x00418d00, 1},
204 { 0x00418e00, 1},
205 { 0x00418e08, 1},
206 { 0x00418e34, 1},
207 { 0x00418e40, 4},
208 { 0x00418e58, 16},
209 { 0x00418f08, 1},
210 { 0x00419000, 1},
211 { 0x0041900c, 1},
212 { 0x00419018, 1},
213 { 0x00419854, 1},
214 { 0x00419864, 1},
215 { 0x00419a04, 2},
216 { 0x00419a14, 1},
217 { 0x00419ab0, 1},
218 { 0x00419ab8, 3},
219 { 0x00419c0c, 1},
220 { 0x00419c8c, 2},
221 { 0x00419d00, 1},
222 { 0x00419d08, 2},
223 { 0x00419e00, 11},
224 { 0x00419e34, 2},
225 { 0x00419e44, 11},
226 { 0x00419e74, 10},
227 { 0x00419ea4, 1},
228 { 0x00419eac, 2},
229 { 0x00419ee8, 1},
230 { 0x00419ef0, 28},
231 { 0x00419f70, 1},
232 { 0x00419f78, 2},
233 { 0x00419f98, 2},
234 { 0x00419fdc, 1},
235 { 0x0041a02c, 2},
236 { 0x0041a0a0, 1},
237 { 0x0041a0a8, 1},
238 { 0x0041a890, 2},
239 { 0x0041a8a0, 3},
240 { 0x0041a8b0, 2},
241 { 0x0041b014, 1},
242 { 0x0041b0a0, 1},
243 { 0x0041b0cc, 1},
244 { 0x0041b1dc, 1},
245 { 0x0041be0c, 3},
246 { 0x0041bea0, 1},
247 { 0x0041becc, 1},
248 { 0x0041bfdc, 1},
249 { 0x0041c054, 1},
250 { 0x0041c2b0, 1},
251 { 0x0041c2b8, 3},
252 { 0x0041c40c, 1},
253 { 0x0041c48c, 2},
254 { 0x0041c500, 1},
255 { 0x0041c508, 2},
256 { 0x0041c600, 11},
257 { 0x0041c634, 2},
258 { 0x0041c644, 11},
259 { 0x0041c674, 10},
260 { 0x0041c6a4, 1},
261 { 0x0041c6ac, 2},
262 { 0x0041c6e8, 1},
263 { 0x0041c6f0, 28},
264 { 0x0041c770, 1},
265 { 0x0041c778, 2},
266 { 0x0041c798, 2},
267 { 0x0041c7dc, 1},
268 { 0x0041c854, 1},
269 { 0x0041cab0, 1},
270 { 0x0041cab8, 3},
271 { 0x0041cc0c, 1},
272 { 0x0041cc8c, 2},
273 { 0x0041cd00, 1},
274 { 0x0041cd08, 2},
275 { 0x0041ce00, 11},
276 { 0x0041ce34, 2},
277 { 0x0041ce44, 11},
278 { 0x0041ce74, 10},
279 { 0x0041cea4, 1},
280 { 0x0041ceac, 2},
281 { 0x0041cee8, 1},
282 { 0x0041cef0, 28},
283 { 0x0041cf70, 1},
284 { 0x0041cf78, 2},
285 { 0x0041cf98, 2},
286 { 0x0041cfdc, 1},
287 { 0x00500384, 1},
288 { 0x005004a0, 1},
289 { 0x00500604, 1},
290 { 0x00500680, 1},
291 { 0x00500714, 1},
292 { 0x0050081c, 1},
293 { 0x00500884, 1},
294 { 0x005008b0, 1},
295 { 0x005008c8, 3},
296 { 0x005008fc, 1},
297 { 0x00500b04, 1},
298 { 0x00500c04, 1},
299 { 0x00500c10, 8},
300 { 0x00500c88, 1},
301 { 0x00500d00, 1},
302 { 0x00500e08, 1},
303 { 0x00500f08, 1},
304 { 0x00501000, 1},
305 { 0x0050100c, 1},
306 { 0x00501018, 1},
307 { 0x00501854, 1},
308 { 0x00501ab0, 1},
309 { 0x00501ab8, 3},
310 { 0x00501c0c, 1},
311 { 0x00501c8c, 2},
312 { 0x00501d00, 1},
313 { 0x00501d08, 2},
314 { 0x00501e00, 11},
315 { 0x00501e34, 2},
316 { 0x00501e44, 11},
317 { 0x00501e74, 10},
318 { 0x00501ea4, 1},
319 { 0x00501eac, 2},
320 { 0x00501ee8, 1},
321 { 0x00501ef0, 28},
322 { 0x00501f70, 1},
323 { 0x00501f78, 2},
324 { 0x00501f98, 2},
325 { 0x00501fdc, 1},
326 { 0x0050202c, 2},
327 { 0x005020a0, 1},
328 { 0x005020a8, 1},
329 { 0x00502890, 2},
330 { 0x005028a0, 3},
331 { 0x005028b0, 2},
332 { 0x00503014, 1},
333 { 0x005030a0, 1},
334 { 0x005030cc, 1},
335 { 0x005031dc, 1},
336 { 0x00503e14, 1},
337 { 0x00503ea0, 1},
338 { 0x00503ecc, 1},
339 { 0x00503fdc, 1},
340 { 0x00504054, 1},
341 { 0x005042b0, 1},
342 { 0x005042b8, 3},
343 { 0x0050440c, 1},
344 { 0x0050448c, 2},
345 { 0x00504500, 1},
346 { 0x00504508, 2},
347 { 0x00504600, 11},
348 { 0x00504634, 2},
349 { 0x00504644, 11},
350 { 0x00504674, 10},
351 { 0x005046a4, 1},
352 { 0x005046ac, 2},
353 { 0x005046e8, 1},
354 { 0x005046f0, 28},
355 { 0x00504770, 1},
356 { 0x00504778, 2},
357 { 0x00504798, 2},
358 { 0x005047dc, 1},
359 { 0x00504854, 1},
360 { 0x00504ab0, 1},
361 { 0x00504ab8, 3},
362 { 0x00504c0c, 1},
363 { 0x00504c8c, 2},
364 { 0x00504d00, 1},
365 { 0x00504d08, 2},
366 { 0x00504e00, 11},
367 { 0x00504e34, 2},
368 { 0x00504e44, 11},
369 { 0x00504e74, 10},
370 { 0x00504ea4, 1},
371 { 0x00504eac, 2},
372 { 0x00504ee8, 1},
373 { 0x00504ef0, 28},
374 { 0x00504f70, 1},
375 { 0x00504f78, 2},
376 { 0x00504f98, 2},
377 { 0x00504fdc, 1},
378 { 0x00900100, 1},
379 { 0x009a0100, 1},
380};
381
382static const u32 gp10b_global_whitelist_ranges_count =
383 ARRAY_SIZE(gp10b_global_whitelist_ranges);
384
385/* context */
386
387/* runcontrol */
388static const u32 gp10b_runcontrol_whitelist[] = {
389};
390static const u32 gp10b_runcontrol_whitelist_count =
391 ARRAY_SIZE(gp10b_runcontrol_whitelist);
392
393static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = {
394};
395static const u32 gp10b_runcontrol_whitelist_ranges_count =
396 ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges);
397
398
399/* quad ctl */
400static const u32 gp10b_qctl_whitelist[] = {
401};
402static const u32 gp10b_qctl_whitelist_count =
403 ARRAY_SIZE(gp10b_qctl_whitelist);
404
405static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = {
406};
407static const u32 gp10b_qctl_whitelist_ranges_count =
408 ARRAY_SIZE(gp10b_qctl_whitelist_ranges);
409
410static const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
411{
412 return gp10b_global_whitelist_ranges;
413}
414
415static int gp10b_get_global_whitelist_ranges_count(void)
416{
417 return gp10b_global_whitelist_ranges_count;
418}
419
420static const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void)
421{
422 return gp10b_global_whitelist_ranges;
423}
424
425static int gp10b_get_context_whitelist_ranges_count(void)
426{
427 return gp10b_global_whitelist_ranges_count;
428}
429
430static const u32 *gp10b_get_runcontrol_whitelist(void)
431{
432 return gp10b_runcontrol_whitelist;
433}
434
435static int gp10b_get_runcontrol_whitelist_count(void)
436{
437 return gp10b_runcontrol_whitelist_count;
438}
439
440static const
441struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void)
442{
443 return gp10b_runcontrol_whitelist_ranges;
444}
445
446static int gp10b_get_runcontrol_whitelist_ranges_count(void)
447{
448 return gp10b_runcontrol_whitelist_ranges_count;
449}
450
451static const u32 *gp10b_get_qctl_whitelist(void)
452{
453 return gp10b_qctl_whitelist;
454}
455
456static int gp10b_get_qctl_whitelist_count(void)
457{
458 return gp10b_qctl_whitelist_count;
459}
460
461static const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void)
462{
463 return gp10b_qctl_whitelist_ranges;
464}
465
466static int gp10b_get_qctl_whitelist_ranges_count(void)
467{
468 return gp10b_qctl_whitelist_ranges_count;
469}
470
471static int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
472{
473 /* Not needed on gp10b */
474 return 0;
475}
476
477void gp10b_init_regops(struct gpu_ops *gops)
478{
479 gops->regops.get_global_whitelist_ranges =
480 gp10b_get_global_whitelist_ranges;
481 gops->regops.get_global_whitelist_ranges_count =
482 gp10b_get_global_whitelist_ranges_count;
483
484 gops->regops.get_context_whitelist_ranges =
485 gp10b_get_context_whitelist_ranges;
486 gops->regops.get_context_whitelist_ranges_count =
487 gp10b_get_context_whitelist_ranges_count;
488
489 gops->regops.get_runcontrol_whitelist =
490 gp10b_get_runcontrol_whitelist;
491 gops->regops.get_runcontrol_whitelist_count =
492 gp10b_get_runcontrol_whitelist_count;
493
494 gops->regops.get_runcontrol_whitelist_ranges =
495 gp10b_get_runcontrol_whitelist_ranges;
496 gops->regops.get_runcontrol_whitelist_ranges_count =
497 gp10b_get_runcontrol_whitelist_ranges_count;
498
499 gops->regops.get_qctl_whitelist =
500 gp10b_get_qctl_whitelist;
501 gops->regops.get_qctl_whitelist_count =
502 gp10b_get_qctl_whitelist_count;
503
504 gops->regops.get_qctl_whitelist_ranges =
505 gp10b_get_qctl_whitelist_ranges;
506 gops->regops.get_qctl_whitelist_ranges_count =
507 gp10b_get_qctl_whitelist_ranges_count;
508
509 gops->regops.apply_smpc_war =
510 gp10b_apply_smpc_war;
511}
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
new file mode 100644
index 00000000..8727951a
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
@@ -0,0 +1,24 @@
1/*
2 *
3 * Tegra GP10B GPU Debugger Driver Register Ops
4 *
5 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __REGOPS_GP10B_H_
20#define __REGOPS_GP10B_H_
21
22void gp10b_init_regops(struct gpu_ops *gops);
23
24#endif /* __REGOPS_GP10B_H_ */
diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
new file mode 100644
index 00000000..f88718b6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
@@ -0,0 +1,150 @@
1/*
2 * GP10B RPFB
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/pm_runtime.h>
17#include <linux/dma-mapping.h>
18#include "gk20a/gk20a.h"
19#include "rpfb_gp10b.h"
20#include "hw_fifo_gp10b.h"
21#include "hw_fb_gp10b.h"
22#include "hw_bus_gp10b.h"
23#include "hw_gmmu_gp10b.h"
24
25int gp10b_replayable_pagefault_buffer_init(struct gk20a *g)
26{
27 u32 addr_lo;
28 u32 addr_hi;
29 struct vm_gk20a *vm = &g->mm.bar2.vm;
30 int err;
31 size_t rbfb_size = NV_UVM_FAULT_BUF_SIZE *
32 fifo_replay_fault_buffer_size_hw_entries_v();
33
34 gk20a_dbg_fn("");
35
36 if (!g->mm.bar2_desc.gpu_va) {
37 err = gk20a_gmmu_alloc_map_sys(vm, rbfb_size,
38 &g->mm.bar2_desc);
39 if (err) {
40 dev_err(dev_from_gk20a(g),
41 "%s Error in replayable fault buffer\n", __func__);
42 return err;
43 }
44 }
45 addr_lo = u64_lo32(g->mm.bar2_desc.gpu_va >> 12);
46 addr_hi = u64_hi32(g->mm.bar2_desc.gpu_va);
47 gk20a_writel(g, fifo_replay_fault_buffer_hi_r(),
48 fifo_replay_fault_buffer_hi_base_f(addr_hi));
49
50 gk20a_writel(g, fifo_replay_fault_buffer_lo_r(),
51 fifo_replay_fault_buffer_lo_base_f(addr_lo) |
52 fifo_replay_fault_buffer_lo_enable_true_v());
53 gk20a_dbg_fn("done");
54 return 0;
55}
56
57void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g)
58{
59 struct vm_gk20a *vm = &g->mm.bar2.vm;
60
61 gk20a_gmmu_unmap_free(vm, &g->mm.bar2_desc);
62}
63
64u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g)
65{
66 u32 get_idx = 0;
67
68 gk20a_dbg_fn("");
69
70 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
71
72 if (get_idx >= fifo_replay_fault_buffer_size_hw_entries_v())
73 dev_err(dev_from_gk20a(g), "%s Error in replayable fault buffer\n",
74 __func__);
75 gk20a_dbg_fn("done");
76 return get_idx;
77}
78
79u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g)
80{
81 u32 put_idx = 0;
82
83 gk20a_dbg_fn("");
84 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
85
86 if (put_idx >= fifo_replay_fault_buffer_size_hw_entries_v())
87 dev_err(dev_from_gk20a(g), "%s Error in UVM\n",
88 __func__);
89 gk20a_dbg_fn("done");
90 return put_idx;
91}
92
93bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g)
94{
95 u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
96 u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
97
98 return (get_idx == put_idx ? true : false);
99}
100
101bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g)
102{
103 u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
104 u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
105 u32 hw_entries = gk20a_readl(g, fifo_replay_fault_buffer_size_r());
106
107 return (get_idx == ((put_idx + 1) % hw_entries) ? true : false);
108}
109
110bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g)
111{
112 u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r());
113
114 return fifo_replay_fault_buffer_info_overflow_f(info);
115}
116
117void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g)
118{
119 u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r());
120
121 info |= fifo_replay_fault_buffer_info_overflow_clear_v();
122 gk20a_writel(g, fifo_replay_fault_buffer_info_r(), info);
123
124}
125
126void gp10b_replayable_pagefault_buffer_info(struct gk20a *g)
127{
128
129 gk20a_dbg_fn("");
130 pr_info("rpfb low: 0x%x\n",
131 (gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) >> 12));
132 pr_info("rpfb hi: 0x%x\n",
133 gk20a_readl(g, fifo_replay_fault_buffer_hi_r()));
134 pr_info("rpfb enabled: 0x%x\n",
135 (gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) & 0x1));
136 pr_info("rpfb size: %d\n",
137 gk20a_readl(g, fifo_replay_fault_buffer_size_r()));
138 pr_info("rpfb get index: %d\n",
139 gp10b_replayable_pagefault_buffer_get_index(g));
140 pr_info("rpfb put index: %d\n",
141 gp10b_replayable_pagefault_buffer_put_index(g));
142 pr_info("rpfb empty: %d\n",
143 gp10b_replayable_pagefault_buffer_is_empty(g));
144 pr_info("rpfb full %d\n",
145 gp10b_replayable_pagefault_buffer_is_full(g));
146 pr_info("rpfb overflow %d\n",
147 gp10b_replayable_pagefault_buffer_is_overflow(g));
148
149 gk20a_dbg_fn("done");
150}
diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h
new file mode 100644
index 00000000..965c9573
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef RPFB_GP20B_H
15#define RPFB_GP20B_H
16struct gk20a;
17
18#define NV_UVM_FAULT_BUF_SIZE 32
19
20int gp10b_replayable_pagefault_buffer_init(struct gk20a *g);
21u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g);
22u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g);
23bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g);
24bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g);
25bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g);
26void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g);
27void gp10b_replayable_pagefault_buffer_info(struct gk20a *g);
28void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g);
29
30#endif
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
new file mode 100644
index 00000000..7f43cb56
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
@@ -0,0 +1,130 @@
1/*
2 * drivers/gpu/nvgpu/gm20b/therm_gk20a.c
3 *
4 * GP10B Therm
5 *
6 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18#include "gk20a/gk20a.h"
19#include "hw_therm_gp10b.h"
20
21static int gp10b_init_therm_setup_hw(struct gk20a *g)
22{
23 u32 v;
24
25 gk20a_dbg_fn("");
26
27 /* program NV_THERM registers */
28 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
29 therm_use_a_ext_therm_1_enable_f() |
30 therm_use_a_ext_therm_2_enable_f());
31 gk20a_writel(g, therm_evt_ext_therm_0_r(),
32 therm_evt_ext_therm_0_slow_factor_f(0x2));
33 gk20a_writel(g, therm_evt_ext_therm_1_r(),
34 therm_evt_ext_therm_1_slow_factor_f(0x6));
35 gk20a_writel(g, therm_evt_ext_therm_2_r(),
36 therm_evt_ext_therm_2_slow_factor_f(0xe));
37
38 gk20a_writel(g, therm_grad_stepping_table_r(0),
39 therm_grad_stepping_table_slowdown_factor0_f(
40 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
41 therm_grad_stepping_table_slowdown_factor1_f(
42 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
43 therm_grad_stepping_table_slowdown_factor2_f(
44 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
45 therm_grad_stepping_table_slowdown_factor3_f(
46 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
47 therm_grad_stepping_table_slowdown_factor4_f(
48 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
49
50 gk20a_writel(g, therm_grad_stepping_table_r(1),
51 therm_grad_stepping_table_slowdown_factor0_f(
52 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
53 therm_grad_stepping_table_slowdown_factor1_f(
54 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
55 therm_grad_stepping_table_slowdown_factor2_f(
56 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
57 therm_grad_stepping_table_slowdown_factor3_f(
58 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
59 therm_grad_stepping_table_slowdown_factor4_f(
60 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
61
62 v = gk20a_readl(g, therm_clk_timing_r(0));
63 v |= therm_clk_timing_grad_slowdown_enabled_f();
64 gk20a_writel(g, therm_clk_timing_r(0), v);
65
66 v = gk20a_readl(g, therm_config2_r());
67 v |= therm_config2_grad_enable_f(1);
68 v |= therm_config2_slowdown_factor_extended_f(1);
69 gk20a_writel(g, therm_config2_r(), v);
70
71 gk20a_writel(g, therm_grad_stepping1_r(),
72 therm_grad_stepping1_pdiv_duration_f(32));
73
74 v = gk20a_readl(g, therm_grad_stepping0_r());
75 v |= therm_grad_stepping0_feature_enable_f();
76 gk20a_writel(g, therm_grad_stepping0_r(), v);
77
78 return 0;
79}
80
81static int gp10b_elcg_init_idle_filters(struct gk20a *g)
82{
83 u32 gate_ctrl, idle_filter;
84 u32 engine_id;
85 u32 active_engine_id = 0;
86 struct fifo_gk20a *f = &g->fifo;
87
88 gk20a_dbg_fn("");
89
90 for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
91 active_engine_id = f->active_engines_list[engine_id];
92 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
93
94 if (tegra_platform_is_linsim()) {
95 gate_ctrl = set_field(gate_ctrl,
96 therm_gate_ctrl_eng_delay_after_m(),
97 therm_gate_ctrl_eng_delay_after_f(4));
98 }
99
100 /* 2 * (1 << 9) = 1024 clks */
101 gate_ctrl = set_field(gate_ctrl,
102 therm_gate_ctrl_eng_idle_filt_exp_m(),
103 therm_gate_ctrl_eng_idle_filt_exp_f(9));
104 gate_ctrl = set_field(gate_ctrl,
105 therm_gate_ctrl_eng_idle_filt_mant_m(),
106 therm_gate_ctrl_eng_idle_filt_mant_f(2));
107 gate_ctrl = set_field(gate_ctrl,
108 therm_gate_ctrl_eng_delay_before_m(),
109 therm_gate_ctrl_eng_delay_before_f(4));
110 gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
111 }
112
113 /* default fecs_idle_filter to 0 */
114 idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
115 idle_filter &= ~therm_fecs_idle_filter_value_m();
116 gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
117 /* default hubmmu_idle_filter to 0 */
118 idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
119 idle_filter &= ~therm_hubmmu_idle_filter_value_m();
120 gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
121
122 gk20a_dbg_fn("done");
123 return 0;
124}
125
126void gp10b_init_therm_ops(struct gpu_ops *gops)
127{
128 gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw;
129 gops->therm.elcg_init_idle_filters = gp10b_elcg_init_idle_filters;
130}
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/therm_gp10b.h
new file mode 100644
index 00000000..18c102fe
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef THERM_GP10B_H
14#define THERM_GP10B_H
15
16struct gpu_ops;
17void gp10b_init_therm_ops(struct gpu_ops *gops);
18
19#endif /* THERM_GP10B_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:55:04 -0500