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authorDebarshi Dutta <ddutta@nvidia.com>2018-08-22 00:27:01 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-29 20:46:51 -0400
commit74639b444251d7adc222400625eb59a3d53d0c0a (patch)
tree19373fbe8ee522863c990fdfa0db24e6474f5167 /drivers/gpu/nvgpu/gp10b
parente3710e5431d8f14f1b8c2812f5c1aeeb7bdaac1c (diff)
gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL
In nvgpu repository, we have multiple accesses to methods in pmu_gk20a.h which have register accesses. Instead of directly invoking these methods, these are now called via HALs. Some common methods such as pmu_wait_message_cond which donot have any register accesses are moved to pmu_ipc.c and the method declarations are moved to pmu.h. Also, changed gm20b_pmu_dbg to nvgpu_dbg_pmu all across the code base. This would remove all indirect dependencies via gk20a.h into pmu_gk20a.h. As a result pmu_gk20a.h is now removed from gk20a.h JIRA-597 Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804283 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c9
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c2
2 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index e66fcff6..8412092a 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -589,6 +589,15 @@ static const struct gpu_ops gp10b_ops = {
589 .pmu_mutex_size = pwr_pmu_mutex__size_1_v, 589 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
590 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, 590 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
591 .pmu_mutex_release = gk20a_pmu_mutex_release, 591 .pmu_mutex_release = gk20a_pmu_mutex_release,
592 .pmu_is_interrupted = gk20a_pmu_is_interrupted,
593 .pmu_isr = gk20a_pmu_isr,
594 .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter,
595 .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,
596 .pmu_read_idle_counter = gk20a_pmu_read_idle_counter,
597 .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter,
598 .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats,
599 .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats,
600 .pmu_enable_irq = gk20a_pmu_enable_irq,
592 .write_dmatrfbase = gp10b_write_dmatrfbase, 601 .write_dmatrfbase = gp10b_write_dmatrfbase,
593 .pmu_elpg_statistics = gp10b_pmu_elpg_statistics, 602 .pmu_elpg_statistics = gp10b_pmu_elpg_statistics,
594 .pmu_init_perfmon = nvgpu_pmu_init_perfmon, 603 .pmu_init_perfmon = nvgpu_pmu_init_perfmon,
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 9851fc5d..033d02c5 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -128,7 +128,7 @@ void mc_gp10b_isr_stall(struct gk20a *g)
128 gk20a_fifo_isr(g); 128 gk20a_fifo_isr(g);
129 } 129 }
130 if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { 130 if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) {
131 gk20a_pmu_isr(g); 131 g->ops.pmu.pmu_isr(g);
132 } 132 }
133 if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { 133 if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
134 g->ops.priv_ring.isr(g); 134 g->ops.priv_ring.isr(g);