gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox size

fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug

Bug 2093809

Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698026
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index a8ee7412..42350dbc 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -80,6 +80,7 @@
 #include <nvgpu/hw/gp10b/hw_top_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
+#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 
 int gp10b_get_litter_value(struct gk20a *g, int value)
 {
@@ -355,6 +356,7 @@ static const struct gpu_ops gp10b_ops = {
                 .get_pmm_per_chiplet_offset =
                         gr_gm20b_get_pmm_per_chiplet_offset,
                 .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
+                .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
         },
         .fb = {
                 .reset = fb_gk20a_reset,