gpu: nvgpu: Reorg fifo HAL initialization

Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the fifo
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522553
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

3 files changed, 88 insertions, 25 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index 633fbfb7..99d9d744 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -80,7 +80,7 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c)
         return 0;
 }
 
-static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
+int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
                         u64 gpfifo_base, u32 gpfifo_entries,
                         unsigned long acquire_timeout, u32 flags)
 {
@@ -147,13 +147,13 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
         return channel_gp10b_commit_userd(c);
 }
 
-static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g)
+u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g)
 {
         return g->gpu_characteristics.gpfifo_class
                 | pbdma_signature_sw_zero_f();
 }
 
-static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
+int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
 {
         u32 new_syncpt = 0, old_syncpt;
         u32 v;
@@ -192,7 +192,7 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
         return 0;
 }
 
-static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
+int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
                                         u32 *inst_id)
 {
         int ret = ENGINE_INVAL_GK20A;
@@ -208,7 +208,7 @@ static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
         return ret;
 }
 
-static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
+void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
                                 u32 *inst_id, u32 *pri_base, u32 *fault_id)
 {
         if (top_device_info_data_type_v(table_entry) ==
@@ -232,7 +232,7 @@ static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
                         top_device_info_data_type_v(table_entry));
 }
 
-static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
+void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
 {
         /*
          * These are all errors which indicate something really wrong
@@ -277,7 +277,7 @@ static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
                 pbdma_intr_0_device_pending_f();
 }
 
-static void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
+void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
         struct mmu_fault_info *mmfault)
 {
         u32 fault_info;
@@ -307,17 +307,3 @@ static void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
         /* note: inst_ptr is a 40b phys addr.  */
         mmfault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v();
 }
-
-void gp10b_init_fifo(struct gpu_ops *gops)
-{
-        gm20b_init_fifo(gops);
-        gops->fifo.get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info;
-        gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc;
-        gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature;
-        gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
-        gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
-        gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
-        gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
-        gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v;
-        gops->fifo.init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs;
-}
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
index da0e82a9..369bed9a 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * GP10B Fifo
  *
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,8 +18,21 @@
 
 struct gpu_ops;
 struct channel_gk20a;
+struct fifo_gk20a;
+struct mmu_fault_info;
 
-void gp10b_init_fifo(struct gpu_ops *gops);
+int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
+                        u64 gpfifo_base, u32 gpfifo_entries,
+                        unsigned long acquire_timeout, u32 flags);
+u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g);
+int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c);
+int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
+                                        u32 *inst_id);
+void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
+                                u32 *inst_id, u32 *pri_base, u32 *fault_id);
+void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
+void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
+        struct mmu_fault_info *mmfault);
 int channel_gp10b_commit_userd(struct channel_gk20a *c);
 
 #endif
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 4479be42..d603703b 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -14,6 +14,7 @@
  */
 
 #include "gk20a/gk20a.h"
+#include "gk20a/fifo_gk20a.h"
 #include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/css_gr_gk20a.h"
 #include "gk20a/bus_gk20a.h"
@@ -43,6 +44,7 @@
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/pmu_gm20b.h"
 #include "gm20b/clk_gm20b.h"
+#include "gm20b/fifo_gm20b.h"
 
 #include "gp10b.h"
 #include "hal_gp10b.h"
@@ -54,6 +56,9 @@
 
 #include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
+#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
+#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
+#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
 
 static int gp10b_get_litter_value(struct gk20a *g, int value)
 {
@@ -210,6 +215,66 @@ static const struct gpu_ops gp10b_ops = {
                 .pg_gr_load_gating_prod =
                         gr_gp10b_pg_gr_load_gating_prod,
         },
+        .fifo = {
+                .init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
+                .bind_channel = channel_gm20b_bind,
+                .unbind_channel = gk20a_fifo_channel_unbind,
+                .disable_channel = gk20a_fifo_disable_channel,
+                .enable_channel = gk20a_fifo_enable_channel,
+                .alloc_inst = gk20a_fifo_alloc_inst,
+                .free_inst = gk20a_fifo_free_inst,
+                .setup_ramfc = channel_gp10b_setup_ramfc,
+                .channel_set_priority = gk20a_fifo_set_priority,
+                .channel_set_timeslice = gk20a_fifo_set_timeslice,
+                .default_timeslice_us = gk20a_fifo_default_timeslice_us,
+                .setup_userd = gk20a_fifo_setup_userd,
+                .userd_gp_get = gk20a_fifo_userd_gp_get,
+                .userd_gp_put = gk20a_fifo_userd_gp_put,
+                .userd_pb_get = gk20a_fifo_userd_pb_get,
+                .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
+                .preempt_channel = gk20a_fifo_preempt_channel,
+                .preempt_tsg = gk20a_fifo_preempt_tsg,
+                .update_runlist = gk20a_fifo_update_runlist,
+                .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
+                .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
+                .wait_engine_idle = gk20a_fifo_wait_engine_idle,
+                .get_num_fifos = gm20b_fifo_get_num_fifos,
+                .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
+                .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
+                .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
+                .force_reset_ch = gk20a_fifo_force_reset_ch,
+                .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
+                .device_info_data_parse = gp10b_device_info_data_parse,
+                .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
+                .init_engine_info = gk20a_fifo_init_engine_info,
+                .runlist_entry_size = ram_rl_entry_size_v,
+                .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
+                .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
+                .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
+                .dump_pbdma_status = gk20a_dump_pbdma_status,
+                .dump_eng_status = gk20a_dump_eng_status,
+                .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
+                .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
+                .is_preempt_pending = gk20a_fifo_is_preempt_pending,
+                .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
+                .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
+                .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
+                .handle_sched_error = gk20a_fifo_handle_sched_error,
+                .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
+                .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
+                .tsg_bind_channel = gk20a_tsg_bind_channel,
+                .tsg_unbind_channel = gk20a_tsg_unbind_channel,
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+                .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
+                .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
+                .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
+                .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
+                .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
+                .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
+#endif
+                .resetup_ramfc = gp10b_fifo_resetup_ramfc,
+                .device_info_fault_id = top_device_info_data_fault_id_enum_v,
+        },
         .mc = {
                 .intr_enable = mc_gp10b_intr_enable,
                 .intr_unit_config = mc_gp10b_intr_unit_config,
@@ -281,6 +346,7 @@ int gp10b_init_hal(struct gk20a *g)
 
         gops->ltc = gp10b_ops.ltc;
         gops->clock_gating = gp10b_ops.clock_gating;
+        gops->fifo = gp10b_ops.fifo;
         gops->mc = gp10b_ops.mc;
         gops->debug = gp10b_ops.debug;
         gops->dbg_session_ops = gp10b_ops.dbg_session_ops;
@@ -340,14 +406,12 @@ int gp10b_init_hal(struct gk20a *g)
         gp10b_init_gr(gops);
         gp10b_init_fecs_trace_ops(gops);
         gp10b_init_fb(gops);
-        gp10b_init_fifo(gops);
         gp10b_init_ce(gops);
         gp10b_init_gr_ctx(gops);
         gp10b_init_mm(gops);
         gp10b_init_pmu_ops(gops);
         gp10b_init_regops(gops);
         gp10b_init_therm_ops(gops);
-        gk20a_init_tsg_ops(gops);
         gk20a_init_pramin_ops(gops);
 
         g->name = "gp10b";